MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 130

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Figure 51: READ Latency (AL = 5, CL = 6)
Mode Register 2 (MR2)
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
BC4
DQS, DQS#
Command
CK#
DQ
CK
ACTIVE n
T0
READ n
t
internally to the DDR3 SDRAM device. READ latency (RL) is controlled by the sum of
the AL and CAS latency (CL), RL = AL + CL. WRITE latency (WL) is the sum of CAS
WRITE latency and AL, WL = AL + CWL (see Mode Register 2 (MR2) (page 130)). Exam-
ples of READ and WRITE latencies are shown in Figure 51 (page 130) and Figure 53
(page 131).
The mode register 2 (MR2) controls additional functions and features not available in
the other mode registers. These additional functions are CAS WRITE latency (CWL), AU-
TO SELF REFRESH (ASR), SELF REFRESH TEMPERATURE (SRT), and DYNAMIC ODT
(R
programmed via the MRS command and will retain the stored information until it is
programmed again or until the device loses power. Reprogramming the MR2 register
will not alter the contents of the memory array, provided it is performed correctly. The
MR2 register must be loaded when all banks are idle and no data bursts are in progress,
and the controller must wait the specified time
sequent operation.
T1
CK. The READ or WRITE command is held for the time of the AL before it is released
TT(WR)
t
RCD (MIN)
). These functions are controlled via the bits shown in Figure 52. The MR2 is
AL = 5
NOP
T2
RL = AL + CL = 11
NOP
T6
130
1Gb: x8, x16 Automotive DDR3 SDRAM
CL = 6
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T11
NOP
t
MRD and
Indicates break
in time scale
NOP
T12
Mode Register 2 (MR2)
DO
n
t
MOD before initiating a sub-
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Transitioning Data
n + 1
DO
NOP
T13
n + 2
DO
n + 3
DO
Don’t Care
NOP
T14