MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 177

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

RESET Operation
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
The RESET signal (RESET#) is an asynchronous reset signal that triggers any time it
drops LOW, and there are no restrictions about when it can go LOW. After RESET# goes
LOW, it must remain LOW for 100ns. During this time, the outputs are disabled, ODT
(R
RESET# being driven HIGH. After RESET# goes HIGH, the DRAM must be re-initialized
as though a normal power-up was executed. All refresh counters on the DRAM are reset,
and data stored in the DRAM is assumed unknown after RESET# has gone LOW.
TT
) turns off (High-Z), and the DRAM resets itself. CKE should be driven LOW prior to
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1Gb: x8, x16 Automotive DDR3 SDRAM
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RESET Operation