MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 182

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Table 80: Dynamic ODT Specific Parameters
Table 81: Mode Registers for R
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
ODTLcwn4
ODTLcwn8
ODTLcnw
Symbol
M9
t
ADC
0
0
0
0
1
1
1
1
MR1 (R
Change from R
Change from R
Change from R
M6
0
0
1
1
0
0
1
1
TT,nom
R
Note:
TT
Description
R
R
TT,nom
TT,nom
change skew
R
)
TT(WR)
• During DRAM operation without READ or WRITE commands, the termination is con-
• When a WRITE command (WR, WRAP , WRS4, WRS8, WRAPS4, WRAPS8) is registered,
ODT is constrained during writes and when dynamic ODT is enabled (see Table 80
(page 182)). ODT timings listed in Table 78 (page 180) also apply to dynamic ODT
mode.
trolled.
– Nominal termination strength R
– Termination on/off timing is controlled via the ODT ball and latencies ODTLon and
and if dynamic ODT is enabled, the ODT termination is controlled.
– A latency of ODTLcnw after the WRITE command: termination strength R
– A latency of ODTLcwn8 (for BL8, fixed or OTF) or ODTLcwn4 (for BC4, fixed or OTF)
– On/off termination timing is controlled via the ODT ball and determined by ODT-
– During the
1. RZQ = 240 . If R
(BC4)
(BL8)
ODTLoff.
switches to R
after the WRITE command: termination strength R
Lon, ODTLoff, ODTH4, and ODTH8.
M2
TT,nom
TT(WR)
TT(WR)
0
1
0
1
0
1
0
1
TT,nom
to
to
to
t
ODTLcnw completed
ADC transition window, the value of R
Write registration
Write registration
Write registration
R
TT(WR)
TT,nom
Reserved
Reserved
RZQ/12
Begins at
RZQ/4
RZQ/2
RZQ/6
RZQ/8
TT,nom
Off
(RZQ)
is used during WRITEs, only RZQ/2, RZQ/4, RZQ/6 are allowed.
182
1Gb: x8, x16 Automotive DDR3 SDRAM
TT,nom
R
R
R
R
R
TT
TT
TT
TT
TT,nom
Micron Technology, Inc. reserves the right to change products or specifications without notice.
switched from R
switched from R
switched from R
Reserved
Reserved
transition complete
is used.
Defined to
120
Off
60
40
20
30
to R
to R
to R
(Ohm)
TT(WR)
TT,nom
TT,nom
TT
TT(WR)
TT,nom
TT(WR)
TT(WR)
is undefined.
R
TT,nom
switches back to R
‹ 2010 Micron Technology, Inc. All rights reserved.
Definition for All
DDR3 Speed Bins
Self refresh, write
4
6
0.5
t
t
CK + ODTL off
CK + ODTL off
Self refresh
Mode Restriction
t
CK ± 0.2
WL - 2
Dynamic ODT
n/a
n/a
n/a
t
CK
TT,nom
TT,nom
Unit
t
t
t
t
CK
CK
CK
CK
.