MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 111

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Figure 39: DLL Disable Mode to DLL Enable Mode
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
Command
ODT
CK#
CKE
CK
ODTLoff + 1 ×
10
7
NOP
T0
t
CK
Notes:
Ta0
SRE
1
The clock frequency range for the DLL disable mode is specified by the parameter
(DLL_DIS). Due to latency counter and timing restrictions, only CL = 6 and CWL = 6 are
supported.
DLL disable mode will affect the read data clock to data strobe relationship (
but not the data strobe to data relationship (
line up read data to the controller time domain.
Compared to the DLL on mode where
cycles after the READ command, the DLL disable mode
after the READ command.
WRITE operations function similarly between the DLL enable and DLL disable modes;
however, ODT functionality is not allowed with DLL disable mode.
10. Static LOW in the case that R
1. Enter SELF REFRESH.
2. Exit SELF REFRESH.
3. Wait
4. Wait
5. Wait
6. Wait
7. Starting with the idle state.
8. Change frequency.
9. Clock must be stable at least
t
CKSRE
NOP
Ta1
t
t
t
t
XS, then set MR1[0] to 0 to enable DLL.
MRD, then set MR0[8] to 1 to begin DLL RESET.
MRD, update registers (CL, CWL, and write recovery may be necessary).
MOD, any valid command.
Tb0
t
CKESR
8
Tc0
111
t
TT,nom
t
CKSRX
CKSRX.
1Gb: x8, x16 Automotive DDR3 SDRAM
Tc1
9
or R
t
DQSCK starts from the rising clock edge AL + CL
Micron Technology, Inc. reserves the right to change products or specifications without notice.
TT(WR)
SRX
Td0
t
DQSQ,
2
is enabled; otherwise, static LOW or HIGH.
t
XS
MRS
Te0
t
QH). Special attention is needed to
3
t
t
MRD
DQSCK starts AL + CL - 1 cycles
Indicates break
in time scale
MRS
Tf0
‹ 2010 Micron Technology, Inc. All rights reserved.
4
t
MRD
t
MRS
DLLK
Tg0
5
Commands
t
Don’t Care
DQSCK)
Valid
Valid
Th0
6
t
CK