MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 7

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Figure 51: READ Latency (AL = 5, CL = 6) ....................................................................................................... 130
Figure 52: Mode Register 2 (MR2) Definition ................................................................................................. 131
Figure 53: CAS Write Latency ........................................................................................................................ 131
Figure 54: Mode Register 3 (MR3) Definition ................................................................................................. 133
Figure 55: Multipurpose Register (MPR) Block Diagram ................................................................................. 134
Figure 56: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout ..................................... 137
Figure 57: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout .......................... 138
Figure 58: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble .................................... 139
Figure 59: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble .................................... 140
Figure 60: ZQ CALIBRATION Timing (ZQCL and ZQCS) ................................................................................. 142
Figure 61: Example: Meeting
Figure 62: Example:
Figure 63: READ Latency .............................................................................................................................. 145
Figure 64: Consecutive READ Bursts (BL8) .................................................................................................... 147
Figure 65: Consecutive READ Bursts (BC4) .................................................................................................... 147
Figure 66: Nonconsecutive READ Bursts ....................................................................................................... 148
Figure 67: READ (BL8) to WRITE (BL8) .......................................................................................................... 148
Figure 68: READ (BC4) to WRITE (BC4) OTF .................................................................................................. 149
Figure 69: READ to PRECHARGE (BL8) .......................................................................................................... 149
Figure 70: READ to PRECHARGE (BC4) ......................................................................................................... 150
Figure 71: READ to PRECHARGE (AL = 5, CL = 6) ........................................................................................... 150
Figure 72: READ with Auto Precharge (AL = 4, CL = 6) ..................................................................................... 150
Figure 73: Data Output Timing –
Figure 74: Data Strobe Timing – READs ......................................................................................................... 153
Figure 75: Method for Calculating
Figure 76:
Figure 77:
Figure 78:
Figure 79:
Figure 80: WRITE Burst ................................................................................................................................ 158
Figure 81: Consecutive WRITE (BL8) to WRITE (BL8) ..................................................................................... 159
Figure 82: Consecutive WRITE (BC4) to WRITE (BC4) via MRS or OTF ............................................................ 159
Figure 83: Nonconsecutive WRITE to WRITE ................................................................................................. 160
Figure 84: WRITE (BL8) to READ (BL8) .......................................................................................................... 160
Figure 85: WRITE to READ (BC4 Mode Register Setting) ................................................................................. 161
Figure 86: WRITE (BC4 OTF) to READ (BC4 OTF) ........................................................................................... 162
Figure 87: WRITE (BL8) to PRECHARGE ........................................................................................................ 163
Figure 88: WRITE (BC4 Mode Register Setting) to PRECHARGE ...................................................................... 163
Figure 89: WRITE (BC4 OTF) to PRECHARGE ................................................................................................ 164
Figure 90: Data Input Timing ........................................................................................................................ 165
Figure 91: Self Refresh Entry/Exit Timing ...................................................................................................... 167
Figure 92: Active Power-Down Entry and Exit ................................................................................................ 171
Figure 93: Precharge Power-Down (Fast-Exit Mode) Entry and Exit ................................................................. 172
Figure 94: Precharge Power-Down (Slow-Exit Mode) Entry and Exit ................................................................ 172
Figure 95: Power-Down Entry After READ or READ with Auto Precharge (RDAP) ............................................. 173
Figure 96: Power-Down Entry After WRITE .................................................................................................... 173
Figure 97: Power-Down Entry After WRITE with Auto Precharge (WRAP) ........................................................ 174
Figure 98: REFRESH to Power-Down Entry .................................................................................................... 174
Figure 99: ACTIVATE to Power-Down Entry ................................................................................................... 175
Figure 100: PRECHARGE to Power-Down Entry ............................................................................................. 175
Figure 101: MRS Command to Power-Down Entry ......................................................................................... 176
Figure 102: Power-Down Exit to Refresh to Power-Down Entry ....................................................................... 176
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
t
t
t
t
RPRE Timing ............................................................................................................................... 154
RPST Timing ............................................................................................................................... 155
WPRE Timing .............................................................................................................................. 157
WPST Timing .............................................................................................................................. 157
t
FAW ............................................................................................................................. 144
t
RRD (MIN) and
t
DQSQ and Data Valid Window .................................................................... 152
t
LZ and
t
HZ ............................................................................................... 154
t
RCD (MIN) ............................................................................. 143
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1Gb: x8, x16 Automotive DDR3 SDRAM
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