MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 128

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Output Drive Strength
OUTPUT ENABLE/DISABLE
TDQS Enable
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
If the DLL is enabled prior to entering self refresh mode, the DLL is automatically disa-
bled when entering SELF REFRESH operation and is automatically reenabled and reset
upon exit of SELF REFRESH operation. If the DLL is disabled prior to entering self re-
fresh mode, the DLL remains disabled even upon exit of SELF REFRESH operation until
it is reenabled and reset.
The DRAM is not tested to check—nor does Micron warrant compliance with—normal
mode timings or functionality when the DLL is disabled. An attempt has been made to
have the DRAM operate in the normal mode where reasonably possible when the DLL
has been disabled; however, by industry standard, a few known exceptions are defined:
• ODT is not allowed to be used
• The output data is no longer edge-aligned to the clock
• CL and CWL can only be six clocks
When the DLL is disabled, timing and functionality can vary from the normal operation
specifications when the DLL is enabled (see DLL Disable Mode (page 109)). Disabling
the DLL also implies the need to change the clock frequency (see Input Clock Frequen-
cy Change (page 113)).
The DDR3 SDRAM uses a programmable impedance output buffer. The drive strength
mode register setting is defined by MR1[5, 1]. RZQ/7 (34 [NOM]) is the primary output
driver impedance setting for DDR3 SDRAM devices. To calibrate the output driver im-
pedance, an external precision resistor (RZQ) is connected between the ZQ ball and
V
The output impedance is set during initialization. Additional impedance calibration up-
dates do not affect device operation, and all data sheet timings and current specifica-
tions are met during an update.
To meet the 34 specification, the output drive strength must be set to 34 during initi-
alization. To obtain a calibrated output driver impedance after power-up, the DDR3
SDRAM needs a calibration command that is part of the initialization and reset proce-
dure.
The OUTPUT ENABLE function is defined by MR1[12], as shown in Figure 50
(page 127). When enabled (MR1[12] = 0), all outputs (DQ, DQS, DQS#) function when in
the normal mode of operation. When disabled (MR1[12] = 1), all DDR3 SDRAM outputs
(DQ and DQS, DQS#) are tri-stated. The output disable feature is intended to be used
during I
leveling) only.
Termination data strobe (TDQS) is a feature of the x8 DDR3 SDRAM configuration that
provides termination resistance (R
TDQS is not supported in x4 or x16 configurations. When enabled via the mode register
(MR1[11]), the R
In contrast to the RDQS function of DDR2 SDRAM, DDR3’s TDQS provides the termina-
tion resistance R
by TDQS; thus, R
SSQ
. The value of the resistor must be 240
DD
characterization of the READ current and during
TT
TT
ON
that is applied to DQS and DQS# is also applied to TDQS and TDQS#.
only. The OUTPUT DATA STROBE function of RDQS is not provided
does not apply to TDQS and TDQS#. The TDQS and DM functions
128
1Gb: x8, x16 Automotive DDR3 SDRAM
TT
) and may be useful in some system configurations.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Mode Register 1 (MR1)
t
DQSS margining (write
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