MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 103

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
10. The DES and NOP commands perform similarly.
11. The power-down mode does not perform any REFRESH operations.
12. ZQ CALIBRATION LONG is used for either ZQinit (first ZQCL command during initializa-
2. RESET# is enabled LOW and used only for asynchronous reset. Thus, RESET# must be
3. The state of ODT does not affect the states described in this table.
4. Operations apply to the bank defined by the bank address. For MRS, BA selects one of
5. “V” means “H” or “L” (a defined logic level), and “X” means “Don’t Care.”
6. See Table 65 (page 104) for additional information on CKE transition.
7. Self refresh exit is asynchronous.
8. Burst READs or WRITEs cannot be terminated or interrupted. MRS (fixed) and OTF BL/BC
9. The purpose of the NOP command is to prevent the DRAM from registering any unwan-
held HIGH during any normal operation.
four mode registers.
are defined in MR0.
ted commands. A NOP will not terminate an operation that is executing.
tion) or ZQoper (ZQCL command after initialization).
103
1Gb: x8, x16 Automotive DDR3 SDRAM
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Commands – Truth Tables
‹ 2010 Micron Technology, Inc. All rights reserved.