MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 129

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

On-Die Termination
WRITE LEVELING
POSTED CAS ADDITIVE Latency
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
share the same ball. When the TDQS function is enabled via the mode register, the DM
function is not supported. When the TDQS function is disabled, the DM function is pro-
vided, and the TDQS# ball is not used. The TDQS function is available in the x8 DDR3
SDRAM configuration only and must be disabled via the mode register for the x4 and
x16 configurations.
ODT resistance R
termination value applies to the DQ, DM, DQS, DQS#, and TDQS, TDQS# balls. DDR3
supports multiple R
12 and RZQ is 240
Unlike DDR2, DDR3 ODT must be turned off prior to reading data out and must remain
off during a READ burst. R
tialized, calibrated, and not performing read access, or when it is not in self refresh
mode. Additionally, write accesses with dynamic ODT enabled (R
places R
The actual effective termination, R
nonlinearity of the termination. For R
nation (ODT) (page 179)).
The ODT feature is designed to improve signal integrity of the memory channel by ena-
bling the DDR3 SDRAM controller to independently turn on/off ODT for any or all devi-
ces. The ODT input control pin is used to determine when R
and off (ODTL off), assuming ODT has been enabled via MR1[9, 6, 2].
Timings for ODT are detailed in On-Die Termination (ODT) (page 179).
The WRITE LEVELING function is enabled by MR1[7], as shown in Figure 50 (page 127).
Write leveling is used (during initialization) to deskew the DQS strobe to clock offset as
a result of fly-by topology designs. For better signal integrity, DDR3 SDRAM memory
modules adopted fly-by topology for the commands, addresses, control signals, and
clocks.
The fly-by topology benefits from a reduced number of stubs and their lengths. Howev-
er, fly-by topology induces flight time skews between the clock and DQS strobe (and
DQ) at each DRAM on the DIMM. Controllers will have a difficult time maintaining
t
which use fly-by topology-based modules. Write leveling timing and detailed operation
information is provided in Write Leveling (page 115).
POSTED CAS ADDITIVE latency (AL) is supported to make the command and data bus
efficient for sustainable bandwidths in DDR3 SDRAM. MR1[4, 3] define the value of AL,
as shown in Figure 51 (page 130). MR1[4, 3] enable the user to program the DDR3
SDRAM with AL = 0, CL - 1, or CL - 2.
With this feature, the DDR3 SDRAM enables a READ or WRITE command to be issued
after the ACTIVATE command for that bank prior to
ACTIVATE to READ or WRITE + AL
(MIN) = CL, a typical application using this feature sets AL = CL - 1
DQSS,
t
DSS, and
TT,nom
with R
TT,nom
t
DSH specifications without supporting write leveling in systems
TT
TT(WR)
termination values based on RZQ/n where n can be 2, 4, 6, 8, or
is defined by MR1[9, 6, 2] (see Figure 50 (page 127)). The R
TT,nom
.
129
termination is allowed any time after the DRAM is ini-
1Gb: x8, x16 Automotive DDR3 SDRAM
TT(EFF)
t
RCD (MIN) must be satisfied. Assuming
TT(EFF)
Micron Technology, Inc. reserves the right to change products or specifications without notice.
, may be different from the R
values and calculations (see On-Die Termi-
t
RCD (MIN). The only restriction is
Mode Register 1 (MR1)
TT
‹ 2010 Micron Technology, Inc. All rights reserved.
is turned on (ODTL on)
TT(WR)
t
CK =
TT
) temporarily re-
targeted due to
t
RCD (MIN) - 1
t
RCD
TT