MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 162

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MT41J64M16JT-15E AIT:G

Manufacturer Part Number
MT41J64M16JT-15E AIT:G
Description
DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
Manufacturer
Micron
Datasheet
Figure 86: WRITE (BC4 OTF) to READ (BC4 OTF)
Command
DQS, DQS#
Address
DQ
CK#
CK
1
3
4
WRITE
Valid
T0
NOP
T1
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2.
3. The BC4 OTF setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and the READ
4. DI n = data-in for column n.
5. BC4, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
NOP
T2
t
command at Tn.
WTR controls the WRITE-to-READ delay to the same device and starts after
WL = 5
NOP
T3
NOP
T4
t
WPRE
NOP
DI
T5
n
n + 1
DI
NOP
n + 2
T6
DI
n + 3
DI
t
WPST
t
BL = 4 clocks
NOP
T7
NOP
T8
NOP
T9
t
BL.
Indicates break
in time scale
T10
NOP
t
WTR
2
Transitioning Data
NOP
T11
READ
Valid
Tn
Don’t Care
RL = 5

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