MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 166

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

PRECHARGE Operation
SELF REFRESH Operation
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
Input A10 determines whether one bank or all banks are to be precharged and, in the
case where only one bank is to be precharged, inputs BA[2:0] select the bank.
When all banks are to be precharged, inputs BA[2:0] are treated as “Don’t Care.” After a
bank is precharged, it is in the idle state and must be activated prior to any READ or
WRITE commands being issued.
The SELF REFRESH operation is initiated like a REFRESH command except CKE is LOW.
The DLL is automatically disabled upon entering SELF REFRESH and is automatically
enabled and reset upon exiting SELF REFRESH.
All power supply inputs (including V
els upon entry/exit and during self refresh mode operation. V
drive V
• V
• V
• The first WRITE operation may not occur earlier than 512 clocks after V
• All other self refresh mode exit timing requirements are met.
The DRAM must be idle with all banks in the precharge state (
bursts are in progress) before a self refresh entry command can be issued. ODT must
also be turned off before self refresh entry by registering the ODT ball LOW prior to the
self refresh entry command (see On-Die Termination (ODT) (page 179) for timing re-
quirements). If R
“Don’t Care.” After the self refresh entry command is registered, CKE must be held LOW
to keep the DRAM in self refresh mode.
After the DRAM has entered self refresh mode, all external control signals, except CKE
and RESET#, are “Don’t Care.” The DRAM initiates a minimum of one REFRESH com-
mand internally within the
The requirements for entering and exiting self refresh mode depend on the state of the
clock during self refresh mode. First and foremost, the clock must be stable (meeting
t
the frequency is not altered while in self refresh mode, then the DRAM is allowed to exit
self refresh mode after
later than when CKE was registered LOW). Since the clock remains stable in self refresh
mode (no frequency change),
clock is altered during self refresh mode (if it is turned-off or its frequency changes),
then
must be satisfied prior to altering the clock's frequency. Prior to exiting self refresh
mode,
When CKE is HIGH during self refresh exit, NOP or DES must be issued for
is required for the completion of any internal refresh already in progress and must be
satisfied before a valid command not requiring a locked DLL can be issued to the de-
vice.
quiring a locked DLL can be applied, a ZQCL command must be issued,
ing must be met, and
CK specifications) when self refresh mode is entered. If the clock remains stable and
SS
REFDQ
t
t
< V
CKSRE and
XS is also the earliest time self refresh re-entry may occur. Before a command re-
t
DDQ
CKSRX must be satisfied prior to registering CKE HIGH.
REFDQ
is valid and stable prior to CKE going back HIGH.
/2 while in self refresh mode under certain conditions:
< V
TT,nom
t
DD
CKSRX must be satisfied. When entering self refresh mode,
is maintained.
t
XSDLL must be satisfied. ODT must be off during
t
and R
CKESR is satisfied (CKE is allowed to transition HIGH
t
CKE period when it enters self refresh mode.
166
TT(WR)
t
CKSRE and
1Gb: x8, x16 Automotive DDR3 SDRAM
are disabled in the mode registers, ODT can be a
REFCA
Micron Technology, Inc. reserves the right to change products or specifications without notice.
and V
t
CKSRX are not required. However, if the
REFDQ
) must be maintained at valid lev-
PRECHARGE Operation
REFDQ
t
‹ 2010 Micron Technology, Inc. All rights reserved.
RP is satisfied and no
may float or not
t
t
XSDLL.
ZQOPER tim-
REFDQ
t
XS time.
t
t
CKESR
CKSRE
is valid.
t
XS