MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 194

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry)
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
There is a transition period around power-down entry (PDE) where the DRAM’s ODT
may exhibit either synchronous or asynchronous behavior. This transition period oc-
curs if the DLL is selected to be off when in precharge power-down mode by the setting
MR0[12] = 0. Power-down entry begins
and ends when CKE is first registered LOW.
1
when CKE goes LOW, power-down entry ends
er than when CKE is first registered LOW. Power-down entry then becomes the greater
of
ODT assertion during power-down entry results in an R
of
(MAX) and ODTLon ×
can result in an R
t
Table 86 (page 195) summarizes these parameters.
If AL has a large value, the uncertainty of the state of R
because ODTLon and ODTLoff are derived from the WL; and WL is equal to CWL + AL.
Figure 114 (page 195) shows three different cases:
• ODT_A: Synchronous behavior before
• ODT_B: ODT state changes during the transition period with
• ODT_C: ODT state changes after the transition period with asynchronous behavior.
AOF (MIN), or as late as the greater of
t
CK or ODTLon + 1
ODTLon ×
t
t
ANPD and
AONPD (MIN) and ODTLon ×
t
CK +
t
RFC - REFRESH command to CKE registered LOW.
TT
t
AON (MIN) and
change as early as the lesser of
t
CK. If a REFRESH command has been issued, and it is in progress
t
CK +
t
AON (MAX). ODT de-assertion during power-down entry
194
t
CK +
1Gb: x8, x16 Automotive DDR3 SDRAM
t
AONPD (MAX) > ODTLon ×
t
t
AOFPD (MAX) and ODTLoff ×
t
Micron Technology, Inc. reserves the right to change products or specifications without notice.
ANPD prior to CKE first being registered LOW,
AON (MIN), or as late as the greater of
t
ANPD.
t
ANPD is equal to the greater of ODTLoff +
t
RFC after the REFRESH command, rath-
t
AOFPD (MIN) and ODTLoff ×
Asynchronous ODT Mode
TT
TT
becomes quite large. This is
change as early as the lesser
‹ 2010 Micron Technology, Inc. All rights reserved.
t
AONPD (MIN) <
t
CK +
t
CK +
t
AON (MAX).
t
AOF (MAX).
t
AONPD
t
CK +