MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 118

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Figure 43: Write Leveling Sequence
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
Early remaining DQ
Late remaining DQ
Differential DQS
Prime DQ
Command
ODT
CK#
CK
4
5
MRS
Notes:
1
t
MOD
NOP
t
2
WLDQSEN
1. MRS: Load MR1 to enter write leveling mode.
2. NOP: NOP or DES.
3. DQS, DQS# needs to fulfill minimum pulse width requirements
4. Differential DQS is the differential data strobe (DQS, DQS#). Timing reference points are
5. DRAM drives leveling feedback on a prime DQ (DQ0 for x4 and x8). The remaining DQ
(MIN) as defined for regular writes. The maximum pulse width is system-dependent.
the zero crossings. The solid line represents DQS; the dotted line represents DQS#.
are driven LOW and remain in this state throughout the leveling procedure.
NOP
t
WLMRD
NOP
t
DQSL
NOP
t
WLH
3
118
T1
NOP
1Gb: x8, x16 Automotive DDR3 SDRAM
Indicates break
in time scale
t
t
t
WLO
WLO
WLO
NOP
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
DQSL
NOP
3
t
WLS
Undefined Driving Mode
NOP
T2
t
DQSH
‹ 2010 Micron Technology, Inc. All rights reserved.
NOP
3
t
t
WLO
DQSH (MIN) and
Write Leveling
NOP
Don’t Care
NOP
t
DQSL