MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 74

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
Notes:
10. The clock’s
11. Spread spectrum is not included in the jitter specification values. However, the input
12. The clock’s
13. The period jitter (
14.
15.
16. The cycle-to-cycle jitter
17. The cumulative jitter error
18.
19. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transi-
1. AC timing parameters are valid from specified T
2. All voltages are referenced to V
3. Output timings are only valid for R
4. The unit
5. AC timing and I
6. All timings that use time-based values (ns, μs, ms) should use
7. Strobe or DQS
8. This output load is used for all AC timing (except ODT reference timing) and slew rates.
9. When operating in DLL disable mode, Micron does not warrant compliance with normal
The unit CK represents one clock cycle of the input clock, counting the actual clock
edges.
ment, but input timing is still referenced to V
AC/DC trip points and CK, CK# and DQS, DQS# use their crossing points). The minimum
slew rate for the input signals used to test the device is 1 V/ns for single-ended inputs
and 2 V/ns for differential inputs in the range between V
correct number of clocks (Table 51 (page 68) uses CK or
the case of noninteger results, all minimum limits are to be rounded up to the nearest
whole integer, and all maximum limits are to be rounded down to the nearest whole
integer.
the rising edge. Clock or CK refers to the CK and CK# differential crossing point when
CK is the rising edge.
The actual test load may be different. The output signal voltage reference point is
V
ure 26 (page 61)).
mode timings or functionality.
MIN is the smallest clock rate allowed, with the exception of a deviation due to clock
jitter. Input clock jitter is allowed provided it does not exceed values specified and must
be of a random Gaussian distribution in nature.
clock can accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz with
an additional 1% of
spectrum may not use a clock rate below
secutive clocks and is the smallest clock half period allowed, with the exception of a de-
viation due to clock jitter. Input clock jitter is allowed provided it does not exceed values
specified and must be of a random Gaussian distribution in nature.
or nominal clock. It is allowed in either the positive or negative direction.
t
rising edge to the following falling edge.
t
ing edge to the following rising edge.
to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL
locking time.
is the amount of clock time allowed to accumulate consecutively away from the average
clock over n number of clock cycles.
t
differential DQS, DQS# slew rate.
tion edge to its respective data strobe signal (DQS, DQS#) crossing.
CH (ABS) is the absolute instantaneous clock high pulse width as measured from one
CL (ABS) is the absolute instantaneous clock low pulse width as measured from one fall-
DS (base) and
DDQ
/2 for single-ended signals and the crossing point for differential signals (see Fig-
Electrical Characteristics and AC Operating Conditions
t
CK (AVG) represents the actual
t
t
CK (AVG) is the average clock over any 200 consecutive clocks and
CH (AVG) and
diff
t
DH (base) values are for a single-ended 1 V/ns DQ slew rate and 2 V/ns
DD
refers to the DQS and DQS# differential crossing point when DQS is
t
JITper) is the maximum deviation in the clock period from the average
tests may use a V
t
CK (AVG) as a long-term jitter component; however, the spread
t
JITcc is the amount the clock period can deviate from one cycle
74
t
CL (AVG) are the average half clock period over any 200 con-
t
ERRnper, where n is the number of clocks between 2 and 50,
1Gb: x8, x16 Automotive DDR3 SDRAM
SS
.
ON34
IL
Micron Technology, Inc. reserves the right to change products or specifications without notice.
-to-V
output buffer selection.
t
t
CK (AVG) of the input clock under operation.
IH
CK (AVG) MIN.
swing of up to 900mV in the test environ-
REF
C
(except
MIN to T
t
CK [AVG] interchangeably). In
t
IL(AC)
IS,
C
MAX values.
t
IH,
‹ 2010 Micron Technology, Inc. All rights reserved.
t
CK (AVG) to determine the
and V
t
DS, and
IH(AC)
.
t
DH use the
t
CK(AVG)