MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 106

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Table 66: READ Command Summary
WRITE
Table 67: WRITE Command Summary
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
Function
READ
READ with
auto
precharge
Function
WRITE
WRITE with
auto
precharge
BL8MRS,
BL8MRS,
BC4MRS
BC4MRS
BL8MRS,
BL8MRS,
BC4OTF
BC4OTF
BC4MRS
BC4MRS
BL8OTF
BL8OTF
BC4OTF
BC4OTF
BL8OTF
BL8OTF
precharge is not selected, the row will remain open for subsequent accesses. The value
on input A12 (if enabled in the mode register) when the READ command is issued de-
termines whether BC4 (chop) or BL8 is used. After a READ command is issued, the
READ burst may not be interrupted.
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA[2:0] inputs selects the bank. The value on input A10 determines whether auto
precharge is used. The value on input A12 (if enabled in the MR) when the WRITE com-
mand is issued determines whether BC4 (chop) or BL8 is used.
Input data appearing on the DQ is written to the memory array subject to the DM input
logic level appearing coincident with the data. If a given DM signal is registered LOW,
the corresponding data will be written to memory. If the DM signal is registered HIGH,
the corresponding data inputs will be ignored and a WRITE will not be executed to that
byte/column location.
Symbol
WRAPS4
WRAPS8
Symbol
RDAPS4
RDAPS8
WRAP
WRS4
WRS8
RDAP
RDS4
RDS8
WR
RD
Cycle
Prev.
Cycle
Prev.
CKE
CKE
H
H
H
H
H
H
H
H
H
H
H
H
Cycle
Next
Cycle
Next
CS# RAS# CAS# WE#
106
CS# RAS# CAS# WE#
L
L
L
L
L
L
L
L
L
L
L
L
1Gb: x8, x16 Automotive DDR3 SDRAM
H
H
H
H
H
H
H
H
H
H
H
H
Micron Technology, Inc. reserves the right to change products or specifications without notice.
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
[3:0]
BA
BA
BA
BA
BA
BA
BA
[3:0]
BA
BA
BA
BA
BA
BA
BA
RFU
RFU
RFU
RFU
RFU
RFU
An
RFU
RFU
RFU
RFU
RFU
RFU
‹ 2010 Micron Technology, Inc. All rights reserved.
An
A12
A12
V
H
V
H
L
L
V
H
V
H
L
L
Commands
A10
A10
H
H
H
L
L
L
H
H
H
L
L
L
A[11,
A[11,
9:0]
9:0]
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA