PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 100

• Manufacturer Part Number: PNX1500E/G,557
• Description: IC MEDIA PROC 240MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1296; 935277746557; PNX1500E/G

Philips Semiconductors
Volume 1 of 1
Table 6: Video/Data Input Operating Modes
PNX15XX_SER_3
Product data sheet
mode
VDI_MODE[1:0] = 0x1
VDI_MODE[1:0] = 0x2
VDI_MODE[1:0] = 0x3
9.2 Video/Data Output Router
In addition to controlling the operating mode of the VDI pins, VDI_MODE[7] bit
controls the activation of a pre-processing module for the 8-bit data that is routed to
the FGPI module. When VDI_MODE[7] = ‘1’ then the input router scans the lower
VDI_D[7:0] inputs for SAV/EAV codes as defined in the video CCIR 656 standard and
uses the ‘start’ and ‘stop’ signals that are routed to the FGPI module as a line and
field detector. FGPI can then be programmed to store in DRAM each field or line at a
specific location which eases the software processing of the data. This processing
stage allows to use of FGPI as a second Video Input as long as ‘on the fly’ pixel
processing is not required.
A subset of the VDI pins can individually be set to operate as GPIO pins in case they
are not used for their primary video/streaming data function.
The output router can provide certain combinations of the following functions:
The VDO pins consist of 39 pins, split into 32 data pins, 2 clock pins and 4 control
signals.
1.
•
•
•
•
•
VIP function
20-bit ITU 656 as for HD video with additional
H&V synchronization signals
8-bit ITU 656
or
8-bit raw data
n/a
Refresh a TFT LCD display up to W-XGA (1280*768) at 60 Hz with RGB 18/24-
bit per pixel.
Refresh progressive or interlaced standard definition video screens using ITU
656 with YUV4:2:2 or 4:4:4 data, with each screen receiving pixels resulting from
the composition and processing of two display surfaces stored in DRAM.
Refresh of a single high-definition
Broadcast of messages to 1 or more receiving PNX15xx Series’s.
Message or unstructured data transmission is in 8-, 16- or 32-bit parallel format,
with data rates up to 100 MHz, providing an aggregate data rate of up to 400
MB/s.
PNX15xx Series does not have the bandwidth and processing power to do a full HDTV decode/
process and HD display, but it can refresh a HD screen and present graphics and video windows
on such a screen.
Rev. 3 — 17 March 2006
1
or VGA resolution screen.
FGPI function
up to 12-bit data capture.
FGPI can be set in 8-, 16-, or 32-bit mode
storing into main memory respectively 8-,
16-, or 32-bit words
up to 24-bit data capture
FGPI is usually set in 32-bit mode storing
32-bit words into main memory.
32-bit data capture.
FGPI is usually set to 32-bit mode.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Chapter 2: Overview
2-19