PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 168

• Manufacturer Part Number: PNX1500E/G,557
• Description: IC MEDIA PROC 240MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1296; 935277746557; PNX1500E/G

Philips Semiconductors
Volume 1 of 1
Table 9: Advantages of Centralized Clock Gating Control
PNX15XX_SER_3
Product data sheet
Logic & s/w point of view
History (existing modules)
Risk
Switching of PLLs/debug
mode
2.8.1 Wake-Up from Power Down
2.8 Power Down
All clocks generated in the clock module may be disabled by programming the
relevant clock enable bit of each clock control register. It is possible to gate module
clocks in individual modules rather than in the Clock Module. The advantages of
centralizing the clock gating are summarized in
To power down all the clocks including the MMIO clock software running on TM3260
must follow this simple procedure.
Remark: The MMIO clock needs to be turned off last but the command needs to come
from the TM3260 so they both need to be turned off together.
More details on the PNX15xx Series powerdown can be found in the
Power
There are three ways to wake up the PNX15xx Series when the MMIO clock is turned
off
1) Wake-up Timer
2) GPIO Interrupt
3) External wake-up signal on GPIO[15]
The wake-up timer is in the clock block and is controlled by the CLK_WAKEUP_CTL.
The wake-up timer is enabled when any value except 0 is written to it. After a value is
written to this register the timer starts counting Xtal clocks (27 MHz) until the value
programmed in the register is reached. Once the value is reached both the MMIO and
the TM3260 clocks are re-activated to 27 MHz.
Clock Gating
in Module
+
-
-
-
1. Power down all the clocks with the exception of the TM3260 CPU clock, clk_tm,
2. Write to the CLK_TM_CTL MMIO register with a value of 0x00000008. This will
and the MMIO clock. Accomplish this by writing a zero to bit 0 of each of the clock
control registers. Before doing so, proper care has to be taken to ensure that the
relevant modules have been disabled.
first turn off the TM3260 clock and later the MMIO clock.
Management.
Clock Gating in
Clock Module
-
+
+
+
Rev. 3 — 17 March 2006
Comments
More logical for s/w to write to Module reg’s to switch
off module_clks
Existing Modules and IP modules are usually not
delivered with clock gating implemented
Clock control is safer being centralized, rather than
scattered in every module
Clocks are already blocked in the clock module during
re-programming of PLLs and dividers or during debug
mode.
Table
9.
Chapter 5: The Clock Module
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Chapter 27
5-17