PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 295

• Manufacturer Part Number: PNX1500E/G,557
• Description: IC MEDIA PROC 240MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1296; 935277746557; PNX1500E/G

Philips Semiconductors
Volume 1 of 1
Table 10: Sampling and Pattern Generation Control Registers for the FIFO Queues
PNX15XX_SER_3
Product data sheet
21
20:18
17:16
Bit
Symbol
EN_DDS_SOURCE
CLOCK_SEL
EN_IO_SEL
Acces
s
R/W
R/W
R/W
Value
0
0
0
Rev. 3 — 17 March 2006
Description
Enables the use of a DDS clock for Signal Sampling or Pattern
Generation using samples and external clock (EN_CLOCK_SEL[26]
= 1) mode:
Note: This field is only valid in Signal Sampling mode
(FIFO_MODE=01) and Pattern Generation using samples mode
(FIFO_MODE=11)
In Signal Sampling / Pattern Generation using samples and external
clock (EN_CLOCK_SEL [26] = 1) mode: This field selects the GPIO
input pin to be used as the external clock. Refer to
field values.
Note: Only the GPIO[6:0] can be used.
Note: If EN_DDS_SOURCE = 1, then, depending on the content of
DDS_OUT_SEL register, one of the GPIO[6:4] pins may receive an
internally generated DDS clock. This clock can then be selected
with CLOCK_SEL.
In Pattern Generation using samples and the frequency divider
(EN_CLOCK_SEL[26] = 0) mode: This field selects which GPIO
output pin to output the sampling frequency clock on. Refer to
Section 4.15
Note: This field is only valid in Signal Sampling mode
(FIFO_MODE=01) and Pattern Generation using samples mode
(FIFO_MODE=11).
Note: The GPIO clock used for sampling or pattern generation must
not be greater than 108 MHz.
This field selects how many GPIO pins should be sampled in one
FIFO queue:
Note: This field is only valid in Signal Sampling mode
(FIFO_MODE=01) or Pattern Generation using samples mode
(FIFO_MODE=11). In all other modes only IO_SEL_0 is enabled.
0 - disabled
1 - enabled
00 - IO_SEL_0 enabled: 1-bit samples
11 - IO_SEL_0 enabled: 1-bit samples
01 - IO_SEL_[1:0] enabled: 2-bit samples
10 - IO_SEL_[3:0] enabled: 4-bit samples
for field values (note only GPIO[6:0] pins can be used).
Chapter 8: General Purpose Input Output Pins
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Section 4.15
for
8-28