PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 691

• Manufacturer Part Number: PNX1500E/G,557
• Description: IC MEDIA PROC 240MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1296; 935277746557; PNX1500E/G

Philips Semiconductors
Volume 1 of 1
Table 2: LAN100 Registers
PNX15XX_SER_3
Product data sheet
Bit
31:0
Offset 0x07 2214
31:0
Offset 0x07 2230/40/50/60 PatternMatch Unit 0/1/2/3 Mask LSBs Register (PatternMatchMask0/1/2/3L)
The PatternMatchMask registers specify a mask for the pattern matching windows so that some bytes can be masked out in
the CRC calculation.
The PatternMatchMask consists of 64 byte-enable signals, one for each byte in the pattern-matching window. The
pattern-matching mask is distributed over two 32-bit registers. The LAN100 has four pattern-matching units.
31:0
Offset 0x07 2234/44/54/64 PatternMatch Unit 0/1/2/3 Mask MSBs Register (PatternMatchMask0/1/2/3H)
The PatternMatchMask registers specify a mask for the pattern matching windows so that some bytes can be masked out in
the CRC calculation.
The PatternMatchMask consists of 64 byte-enable signals, one for each byte in the pattern-matching window. The pattern
matching mask is distributed over two 32-bit registers. The LAN100 has four pattern-matching units.
31:0
Offset 0x07 2238/48/58/68 PatternMatch Unit 0/1/2/3 CRC Register (PatternMatchCRC0/1/2/3)
Each of the four pattern-matching filters calculates a 32-bit CRC on a 64-byte window. If the CRC matches the 32-bit golden
CRC value in the filter unit’s CRC register, a match is found.
31:0
Offset 0x07 223C/4C/5C/6C PatternMatch Unit 0/1/2/3 Skip Bytes (PatternMatchSkip0/1/2/3)
Each of the four pattern-matching filters calculates a 32-bit CRC on a 64-byte window. The window can have an offset with
respect to the start of the frame. The Pattern Match Unit 0/1/2/3 Skip Bytes register specifies the number of bytes that must
be skipped before starting the window.
31:0
Offset 0x07 2FE0
The interrupt status register is read-only. Bits can be set via the IntSet register. Bits can be cleared via the IntClear register.
31:14
13
12
11
10
9
8
Symbol
HashFilterL
HashFilterH
PatternMatchMask0/1/2/
3L
PatternMatchMask0/1/2/
3H
PatternMatchCRC0/1/2/
3
PatternMatchSkip0/1/2/3 R/W
-
WakeupInt
SoftInt
TxRtDoneInt
TxRtFinishedInt
TxRtErrorInt
TxRtUnderrunInt
Hash filter table MSBs register (HashFilterH)
Interrupt Status Register (IntStatus)
…Continued
Acces
s
R/W
R/W
R/W
R/W
R/W
-
RO
RO
RO
RO
RO
RO
Value
Rev. 3 — 17 March 2006
Description
Bit 31:0 of the imperfect filter hash table for receive filtering.
Bit 63:32 of the imperfect filter hash table for receive filtering.
Bits 31:0 of the pattern-matching mask for filter unit 0/1/2/3. Each bit
represents a byte-enable in the pattern-matching window.
Bits 63:32 of the pattern-matching mask for filter unit 0/1/2/3. Each
bit represents a byte-enable in the pattern-matching window.
The golden CRC for pattern-matching filter unit 0/1/2/3.
The number of bytes in a frame that need to be skipped before
starting pattern-matching filtering in unit 0/1/2/3.
Unused
Interrupt was triggered by a Wakeup event detected by the receive
filter.
Interrupt was triggered by software writing a 1 in the IntSet register.
Interrupt was triggered because a real-time descriptor was
transmitted and the Interrupt bit in its descriptor was set.
Interrupt was triggered because all real-time descriptors have been
processed, so that now ProduceIndex == ConsumeIndex.
Interrupt was triggered on real-time transmit errors: LateCollision,
ExcessiveCollision, ExcessiveDefer, and NoDescriptor or Underrun.
Interrupt set on a fatal underrun error in the real-time transmit
queue. The fatal interrupt should be resolved by a Tx soft-reset. The
bit is not set in case of a non fatal underrun error.
Chapter 23: LAN100 — Ethernet Media Access Controller
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
23-22