PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 467

• Manufacturer Part Number: PNX1500E/G,557
• Description: IC MEDIA PROC 240MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1296; 935277746557; PNX1500E/G

Philips Semiconductors
Volume 1 of 1
Table 1: Module signal pins
PNX15XX_SER_3
Product data sheet
Signal
fgpo_stop
or
fgpo_buf_start
fgpo_data
fgpo_interrupt
Type
output
output
output
2.1 Reset
2.2 Base Addresses
2.3 Sample (data) Size
FGPO is reset by any PNX15xx Series system reset or by setting the
SOFTWARE_RESET bit FGPO_SOFT_RST register.
Remark: SOFTWARE_RESET does not reset MMIO bus interface registers. Any
DMA transfers will be aborted during a SOFTWARE_RESET. All registers reset to the
Reset Value shown in the Register Description section.
Two base address registers are used to point to main memory buffers in a double
buffering scheme. Addresses are forced into 32-bit address alignment.
Data size (width) per sample is set to either 8, 16, or 32-bit using
FGPO_CTL.DATA_SIZE bit field. For 8-bit samples, four samples are packed into one
32-bit word. For 16-bit samples, two samples are packed 2 into one 32-bit word.
Packed data is read from memory in full 32-bit words.
Byte order, with which the data is read from memory, is controlled by the global
PNX15xx Series endian mode. The endian state only affects 16 and 32-bit sample
sizes.
…Continued
Description
To External PAD VDO_D[33] via Output Router.
Message Passing Mode:
A programmable pulse on fgpo_stop indicates the end of a message. This pulse may be
programmed to be a one clock pulse concurrent with the last data sample, or a pulse lasting
as long as valid data samples are output.
Record Capture Mode:
A programmable pulse on fgpo_buf_start indicates the start of a new buffer. The pulse may
be programmed to occur one clock before or at the same clock with the first valid data sample
for the buffer
or
A positive pulse lasting as long as each buffer is active.
or
A positive pulse lasting as long as buffer 2 is active.
To External PAD VDO_D[31:0] via Output Router.
General Purpose high speed sample data output changing on each active edge of clk_fgpo.
In 8-bit mode data is placed on fgpo_data7:0]. In 16-bit mode data is placed on
fgpo_data[15:0].
Interrupt status connects to the TriMedia Processor in the PNX15xx Series.
Rev. 3 — 17 March 2006
Chapter 13: FGPO: Fast General Purpose Output
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
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