PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 125

• Manufacturer Part Number: PNX1500E/G,557
• Description: IC MEDIA PROC 240MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1296; 935277746557; PNX1500E/G

Philips Semiconductors
Volume 1 of 1
Table 7: TM3260 System Parameters MMIO Registers
7. Video Input and Output Routers
PNX15XX_SER_3
Product data sheet
System Module Registers
Offset 0x06 3700
31:4
3
2
1
0
Offset 0x06 3704
31:1
0
Bit
Symbol
Unused
TM32_APERT_MODIFI
ABLE
TM32_LS_DBLLINE
TM32_IFU_DBLLINE
TM32_PWRDWN_REQ
Unused
TM32_PWRDWN_ACK
6.3.1 TM3260
TM32_CONTROL
TM32_STATUS
PNX15xx Series provides two groups of high speed pins to stream data or video in
and out. The input group of pins is prefixed by VDI, Video Data Input. The output
group is prefixed by VDO, Video Data Output. Each group is shared between two
modules. On the input side, VIP and FGPI get their pin allocation through the input
router. On the output side QVCP and FGPO get their pin assignment through the
output router. The input router is controlled by VDI_MODE. The output router is
controlled by the VDO_MODE.
Acces
s
-
R/W
R/W
R/W
R/W
-
R
System Parameters MMIO Registers
Value
-
0x1
0x1
0x1
0x0
-
0x0
Rev. 3 — 17 March 2006
Description
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
TM3260 Aperture Modifiable.
This bit is usually written once at boot time.
The value of this bit can only be altered once.
TM3260 Load/Store Unit (i.e. Data Cache) Double Line Fill enable
TM3260 Instruction Fetch Unit (i.e. Instruction Cache) Double Line
Fill enable
TM3260 full powerdown request
Upon writes:
Upon reads
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
0: TM3260 is in full power mode.
1: TM3260 is in full powerdown mode.
• 0: Disables writes by the TM3260 to the MMIO registers
• 1: Enables writes by the TM3260 to the MMIO registers
• 0: Do not enable Double Line fills for the Load/Store Unit
• 1: Enable Double Line fills for the Load/Store Unit
• 0: Do not enable Double Line fills for the Instruction Fetch Unit
• 1: Enable Double Line fills for the Instruction Fetch Unit
• 1->0: Request a TM3260 Power Up
• 0->1: Request a TM3260 Power Down
• Undefined
TM32_DRAM_HI, TM32_DRAM_LO, TM32_APERT_HI and
TM32_APERT_LO.
TM32_DRAM_HI, TM32_DRAM_LO, TM32_APERT_HI and
TM32_APERT_LO.
Chapter 3: System On Chip Resources
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
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