PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 663

• Manufacturer Part Number: PNX1500E/G,557
• Description: IC MEDIA PROC 240MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1296; 935277746557; PNX1500E/G

Philips Semiconductors
Volume 1 of 1
4. Application Notes
5. Register Descriptions
Table 9:
PNX15XX_SER_3
Product data sheet
Offset
0x07 5000
0x07 5004
0x07 5008
0x07 500C
0x07 5010
0x07 5014
0x07 5018
Register Summary
Symbol
VLD_COMMAND
VLD_SR
VLD_QS
VPD_PI
VLD_MC_STATUS
VLD_IE
VLD_CTL
4.0.1 PNX1300 Series versus PNX15xx Series VLD
5.1 PNX1300 Series and PNX15xx Series Register Differences
5.2 VLD Register Summary
The current VLD is a compatible superset of the VLD that was implemented in the
PNX1300 Series chip. Differences in the register definitions are noted in
text.
The PNX15xx Series implementation removed the RL/MBH write-back DMA
channels. Differences from the current VLD implementation are noted in
The base address for the PNX15xx Series VLD module is 0x07 5000.
•
•
•
•
•
The MPEG-2 Macroblock Header Output Format now differs in two ways: the
First Forward Motion Vector bit[1] which was unused is now the “First Macro
Block” bit, and the sixth word bits[23:16] now contain the Slice Start Code.
The PNX1300 Series does not implement the “Parse Long” command.
In the VLD_STATUS register, the PNX1300 Series does not implement the
following bits:
–
In the VLD_CONTROL register, the PNX1300 Series does not implement the
following bits:
–
–
–
In addition, the Little_Endian mode bit is on bit[1] in the PNX1300 Series; but it is
bit[0] in this module.
Bit[6] RL Overflow
Bit[16] Slice_strobe
Bit[15:8] Slice_start_code
Bit[2] DMA_input_done_mode
Description
Variable Length Decoder Command
VLD Shift Register (shadow)
Quantization Scale Code to be output by the VLD
VLD Picture Information
VLD and MC Status register
VLD Interrupt Enable
VLD Control register
Rev. 3 — 17 March 2006
Chapter 21: MPEG-1 and MPEG-2 Variable Length Decoder
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
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