PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 127

• Manufacturer Part Number: PNX1500E/G,557
• Description: IC MEDIA PROC 240MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1296; 935277746557; PNX1500E/G

Philips Semiconductors
Volume 1 of 1
Table 8: Global Registers
PNX15XX_SER_3
Product data sheet
Input and Output Control Registers
Offset 0x06 3000
31:8
7
6:5
Bit
Symbol
Unused
VDI_MODE_7
Unused
VDI_MODE
Acces
s
-
R/W
-
Value
-
0
-
Rev. 3 — 17 March 2006
Description
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
This bit should be set to ‘1’ only when FGPI is set to work in 8-bit
mode.
This bit controls dedicated hardware located in the input router that
allows to use the FGPI module as a second module to capture a
656 video source. However in this mode there is no on-the-fly video
image processing possible and the YUV data is linearly stored in
memory (VIP uses YUV planes). The dedicated hardware allows to
generate fgpi_start and fgpi_stop signals that directs FGPI to store
each field of the in-coming 656 video stream into a separate buffer.
The description bellow explains the behavior of the state machine
for that dedicated pattern matching hardware.
0: Disable pattern matching state machine for FGPI start/stop
signals.
1: Enable pattern matching state machine for FGPI start/stop
signals.
When first enabled, the pattern matching state machine is in its
“INIT” state and begins comparing fgpi_data[7:0] for the pattern
0xFF, 0x00, 0x00, and 0xEC on each fgpi clock. Once this pattern is
detected, it enters the “MAIN” state.
Below are listed the patterns for fgpi_start and fgpi_stop signal
assertion/de-assertion when in the MAIN state. The fgpi_start
signal asserts for one fgpi clock when the fourth byte of the pattern
is matched. The fgpi_start signal de-asserts on the next fgpi clock
and remains de-asserted until one of the patterns is detected. The
fgpi_stop asserts when the assertion pattern is detected and
remains asserted until the de-assertion pattern is detected. The
pattern matching state machine returns to the “INIT” state when
VDI_MODE[7] = 0 or the FGPI block is reset with a Hardware or
Software reset.
fgpi_start = 1 when fgpi_data[7:0] =0xFF, 0x00, 0x00, 0x9D or
0xFF, 0x00, 0x00, 0xDA or
0xFF, 0x00, 0x00, 0xF1 or
0xFF, 0x00, 0x00, 0xB6
else fgpi_start = 0.
fgpi_stop = 1 when fgpi_data[7:0] =0xFF, 0x00, 0x00, 0xF1
fgpi_stop = 0 when fgpi_data[7:0] =0xFF, 0x00, 0x00, 0xB6
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
Chapter 3: System On Chip Resources
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
3-18