PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 199

• Manufacturer Part Number: PNX1500E/G,557
• Description: IC MEDIA PROC 240MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1296; 935277746557; PNX1500E/G

Philips Semiconductors
Volume 1 of 1
Table 11: CLOCK MODULE REGISTERS
PNX15XX_SER_3
Product data sheet
Bit
5
4:3
2:1
0
Offset 0x04,7418
31:6
5
4
3
2:1
0
Offset 0x04,741C-0x04,74FCReserved
Debug Registers
Offset 0x04,7500
Symbol
fgpo_output_enable_n
sel_clk_fgpo_src
sel_clk_fgpo
en_clk_fgpo
Reserved
turn_off_ack
fgpi_output_enable_n
sel_clk_fgpi_src
sel_clk_fgpi
en_clk_fgpi
CLK_FGPI_CTL
CLK_STRETCHER_CTL
Acces
s
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
…Continued
Value
1
00
00
1
-
0
1
0
00
1
Rev. 3 — 17 March 2006
Description
FGPO output enable
0: output, the clock is generated internally
1: input, the clock is provided by an external source. Note: during
and after reset the xtal clock is forced onto the fgpo clock. In order
to actually allow the input clock to go to the fgpo this register must
be written to. This also implies that writing fgpo_output_enable_n =
1 overrides a sel_fgpo_clk = 0.
00: clk_fgpo_src = PLL1
01: clk_fgpo_src = UNDEF
10: clk_fgpo_src = DDS2
11: clk_fgpo_src = clk_tm (It is not meant to be used in normal
operating mode. The observation is after the output of the duty cycle
stretcher, therefore it is the clock that feeds the TM3260).
The following 4 settings are valid when fgpo_output_enable_n = 0
(either of the two output modes).
00: clk_fgpo = 27 MHz xtal_clk
01: clk_fgpo = clk_fgpo_src
10: clk_fgpo = clk_fgpo_src
11: clk_fgpo = LAN_RXD[2]
The following 3 settings are valid when fgpo_output_enable_n = 1
(the input mode).
01: clk_fgpo = VDO_CLK2
1: enable clk_fgpo
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
Fgpi output enable
0: output, the clock is generated internally
1: input, the clock is provided by an external source unless
sel_fgpi_clk is 00 then it is xtal clock.
0: clk_fgpi_src = DDS3
1: clk_fgpi_src = DDS8
00: clk_fgpi = 27 MHz xtal_clk (voids fgpi_output_enable_n)
Only used when fgpi_output_enable_n = 0 :
01: clk_fgpi = clk_fgpi_src
10: clk_fgpi = clk_fgpi_src
11: clk_fgpi = LAN_RXD[3]
1: enable clk_fgpi
Chapter 5: The Clock Module
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
5-48