PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 714

• Manufacturer Part Number: PNX1500E/G,557
• Description: IC MEDIA PROC 240MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1296; 935277746557; PNX1500E/G

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
Figure 7:
MMIO cmd.
MMIO write data
Descriptor read cmd.
Descriptor read data
Descriptor read last
Data read command
Data read data
Data read last
MII transmit data
Write status cmd.
Status write data
Write status last
Write status tag
Status write tag ack.
Tx(Rt)ProduceIndex
Tx(Rt)ConsumeIndex
Transmit example waves
0
5.5 Receive process
Issue descriptor read and
status write commands
MMIO write produce index 3
Figure 7
for this example.
Each byte transferred from memory is transmitted across the MII Interface as a byte,
and the MII interface hardware adds the preamble, frame delimiter leader, and the
CRC trailer, if hardware CRC is enabled. Once transmission on the MII Interface
commences, the transmission cannot be interrupted without generating an underrun
error, which is why descriptors and data read commands are issued as soon as
possible and are pipelined. In 10Mb/s and 100Mb/s mode, the output signals look
similar, but in 10Mb/s mode, the transmit clock is scaled down by a factor 10.
In case an RMII PHY is connected, the data communication between the MII
Interface and the PHY is communicated at half the data-width and twice the clock
frequency (50 MHz). In
doubled in the 100Mb/s mode. In 10Mb/s mode, data will only be transmitted once
every 10 clock cycles (an clock gate disables the 50MHz clock for the intervening nine
cycles).
This section outlines the receive process including the activities in the device driver
software.
Issue data read
Issue data
returned
Descriptor read data returned
Start transmission
depicts the memory transactions and the transactions on the MII interface
Preamble
Rev. 3 — 17 March 2006
Chapter 23: LAN100 — Ethernet Media Access Controller
Figure
0
Write first
fragment status
Tag status
7, the frequency of the MII transmit data signal will be
3
Wait for tag acknowledge
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Update
consume
register
1
CRC
End transmission
2
3
23-45