PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 563

• Manufacturer Part Number: PNX1500E/G,557
• Description: IC MEDIA PROC 240MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1296; 935277746557; PNX1500E/G

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
3.1.4 SPDIF Input and the Oversampling Clock
3.2.1 SPDIF Input Register Set
3.2 Register Programming Guidelines
or 0.26UI pk-pk (1 UI = 1/128 Fs ). For a particular Fs , the max jitter is shown in
Table
Table 2: Input Jitter for Different Sample Rates
The SPDIF Input receiver will reproduce the input data and clock without error if the
maximum input jitter remains within the specified max jitter tolerance above. The
receiver design meets and exceeds the IEC60958-3 consumer jitter requirements
specification (i.e 0.25 UI pk-pk between 200 Hz and 400 kHz jitter freq. ).
The oversampling clock supplied to the input receiver is derived from a divider in the
central clock control block. The divider value to select is determined by
the oversampling clock has been selected by programming a divider value, the
condition of the LOCK bit status indicator in SPDI_STATUS provides feedback on
whether the selected oversampling clock has allowed the interface to achieve lock
onto the incoming SPDIF input stream. The settings provided by the divider for the
oversampling clock are sufficient for capture of 32 kHz, 44.1 kHz, 48 kHz and 96 kHz
sample rate input streams.
The S/PDIF register set is outlined in
page
to configure SPDIF Input data capture and DMA of audio data to main memory. To
ensure compatibility with future devices, any reserved MMIO register bits in
and
Fs (kHz)
32
44.1
48
96
Figure 6:
Figure 10
SPDI_IN
18-16. The register set is composed of status and control functions necessary
2.
SPDIF Input domain
Central clocking domain
PIN
SPDIF Input Oversampling Clock Generation
should be ignored when read, and written as zeroes .
Rev. 3 — 17 March 2006
1 UI = 1/(128 Fs) (nsec)
244.1
177.2
162.8
81.4
SPDIF Input
Receiver
oversampling
clock
Figure 9 on page 18-15
Divide by n
n = 3, 6
SPDIF Input
Decoder
Max Jitter = 0.26UI pk-pk (nsec)
31.7
23.0
21.2
10.6
432MHz (16x27MHz)
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Chapter 18: SPDIF Input
and
Figure 10 on
Memory Bound
Audio Data
Table
Figure 9
1. Once
18-7