PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 314

• Manufacturer Part Number: PNX1500E/G,557
• Description: IC MEDIA PROC 240MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1296; 935277746557; PNX1500E/G

1. Introduction
2. Functional Description
The DDR Controller is used to interface to off-chip DDR memory.
The primary features of the DDR SDRAM Controller include:
The DDR controller module includes an arbiter which arbitrates between the DDR
burst commands coming from the two different MTL ports. After arbitration, the DDR
burst command selected by the arbiter is put in a 5-entry FIFO. The DDR module has
a refresh counter to keep track of the refresh timing. The DDR module keeps track of
the open pages in the DDR memories. Up to two DDR ranks (with 4 banks each) are
supported resulting in a total of eight pages. The DDR command generator decides
upon which command (refresh, precharge, activate, read, or write) to generate based
on the information in the 5-entry FIFO, the state of the refresh counter, and the state
of the DDR memories as indicated by the open page table.
The PNX15xx Series DDR controller follows the JEDEC specifications, [1][2].
Refer to
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Chapter 9: DDR Controller
PNX15xx Series Data Book – Volume 1 of 1
Rev. 3 — 17 March 2006
16- or 32-bit data bus width on DDR SDRAM memory side
two MTL ports (one for the DMA memory traffic, one for the CPU)
Supports x8, x16 and x32 memory devices
Supports 64-Mbit, 128-Mbit, 256-Mbit and 512-Mbit DDR SDRAM memory
devices
Supports up to 2 ranks (physical banks) of memory devices
Maximum of 8 open pages
Maximum address range of 256 MBytes
Halt modes to allow for power consumption reduction
Programmable DDR SDRAM timing parameters that support DDR SDRAM
memory devices up to 200 MHz
Programmable bank mapping scheme to potentially improve bandwidth utilization
(see
Chapter
Section
2.3.1).
for electrical and load constraints.
Product data sheet