PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 64

• Manufacturer Part Number: PNX1500E/G,557
• Description: IC MEDIA PROC 240MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1296; 935277746557; PNX1500E/G

Philips Semiconductors
Volume 1 of 1
Table 33: QVCP, LCD and FGPO Timing With Internal Clock Generation
Table 34: QVCP, LCD and FGPO Timing With External Clock Generation
PNX15XX_SER_3
Product data sheet
Symbol
F
F
T
T
T
Symbol
F
F
T
T
T
QVCP
FGPO
CLK-DV
SU-CLK
H-CLK
QVCP
FGPO
CLK-DV
SU-CLK
H-CLK
Parameter
VDO_CLK1 frequency
VDO_CLK2 frequency
Clock to VDO_D[34:0] and VDO_AUX for PNX1502
Clock to VDO_D[34:0] and VDO_AUX for PNX1501
Clock to VDO_D[34:0] and VDO_AUX for PNX1500
Input setup time
Input hold time
Parameter
VDO_CLK1 frequency
VDO_CLK2 frequency
Clock to VDO_D[34:0] and VDO_AUX
Input setup time
Input hold time
7.4 QVCP, LCD and FGPO Interfaces
[33-1]
[33-2]
[33-3]
[33-4]
[33-5]
[33-6]
See timing measurement conditions
Timing applies when the data is output on a positive or a negative edge in double edge clock
mode, see
If the VDO_CLK[1,2] is inverted internally then the timing applies to the negative edge.
Timing applies for VDO_D[29], FGPO_REC_SYNC and FGPO_BUF_SYNC. VDO_D[29]
and FGPO_BUF_SYNC. This inputs are assumed asynchronous.
In double edge clock mode, the maximum VDO_CLK1 frequency is lower than in single edge
clock mode. Refer to
The SAA7104H/5H input hold time specification for the data lines, PD[11:0], is actually 1.2
ns. The SAA7104H/5H input hold time specification for the xSVGC lines (SYNC signals)
remains 1.5 ns; therefore traces on the board should compensate for the missing 0.3 ns
delay.
Table 1 on page
Rev. 3 — 17 March 2006
Section 4.
3-6.
for differences in between the different devices.
Figure
Min
1.2
1.2
1.2
3
2
Min
3
4
4
12.
Chapter 1: Integrated Circuit Data
Max
Section 4.
100
Max
81
81
3.5
3.8
4.4
11
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Units
MHz
MHz
ns
ns
ns
ns
ns
Units
MHz
MHz
ns
ns
ns
Notes
5
1, 2, 3, 6
1, 2, 3, 6
1, 2, 3, 6
1, 2, 3, 4
1, 2, 3, 4
Notes
5
5
1, 2, 3
1, 2, 3, 4
1, 2, 3, 4
1-37