PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 786

• Manufacturer Part Number: PNX1500E/G,557
• Description: IC MEDIA PROC 240MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1296; 935277746557; PNX1500E/G

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
1.1.3 Peripheral Module Wakeup Sequence
1.1.4 TM3260 Powerdown Modes
Remark: This bit does NOT gate the internal module clock or other clocks as clock
gating is not allowed inside a module.
Waking up a module is also under CPU control and is the reverse sequence to
powerdown:
The TM3260 CPU has two modes: Partial Powerdown and Full Powerdown.
Partial Powerdown Mode
The TM3260 CPU enters partial powerdown mode by performing a 'store' to a
specific MMIO address (the POWERDOWN register). The TM3260 then finishes any
pending transactions and go into a partial powerdown. In partial powerdown mode,
cycle counters, timers and interrupt logic in the TM3260 are still active. The TM3260
CPU wakes up from partial powerdown when an interrupt occurs or there is an
access to its MMIO space. This commonly used by the idle task in an operating
system.
Full Powerdown Mode
The TM3260 also have an externally-initiated full power shutdown mode i.e., no
wakeups when an interrupt occurs. Entering this mode is requested by asserting an
input signal to the TM3260. When this signal is asserted, the TM3260 finishes
pending transactions and gates-off its core clock.
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The CPU writes/sets the device's POWERDOWN control bit (usually bit 31 of
offset 0xFF4). Setting this bit causes the device to power down elements such as
memories and register files.
After setting the powerdown bit, none of the device's registers is accessible,
except the one containing the POWERDOWN bit, which is 100% operational.
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The CPU programs the Clock module to stop/slow down the clock signals. This
assures the Clock module is stopped in a controlled way (no glitches/illegal
periods).
At this point, the register with the POWERDOWN bit is still the only accessible
register and the block is fully powered down.
Program the Clock module so that all related clock sources are set to their normal
operational frequencies.
Reset the POWERDOWN bit in the module.
Set up the module's configuration registers if needed.
Enable the module.
Reads from any other register do not hang.
Writes to any register (except the POWERDOWN bit register) are completed
fully or result in an error.
Rev. 3 — 17 March 2006
Chapter 27: Power Management
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
27-2