PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 113

• Manufacturer Part Number: PNX1500E/G,557
• Description: IC MEDIA PROC 240MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1296; 935277746557; PNX1500E/G

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
Figure 2:
MMIO_BASE/base_14
TM32_DRAM_CLIMIT
TM32_APERT1_LO
TM32_APERT1_HI
TM32_DRAM_LO
TM32_DRAM_HI
0x1 0000 0000
0x0000 0000
PNX15xx Series System Memory Map
2MB
non-cacheable
APERT1 Aperture
2.3 The DCS View Or The System View
DRAM Aperture
MMIO Aperture
inaccessible
inaccessible
inaccessible
inaccessible
TM3260
Remark: If the value 0x0000,0000 is stored into TM32_APERT1_HI, this value is
understood as 0x1,0000,0000.
The DCS bus can be seen as the link between the PCI side and the CPU side:
Remark: Requests from the TM3260 to APERT1 may fall in an non accessible
address region in the DCS bus, like between the PCI1 and PCI2 apertures. It is legal
to do so. The request is discarded by the DCS bus controller and a random value is
returned upon reads.
Remark: TM3260 compiler uses speculative loads (i.e. the result of the load may not
be used by the CPU) to improve performance. These speculative loads often contain
addresses coming from the TM3260 internal register file that are not initialized
properly since the return value of the load is not to be used (unless the execution of
•
•
Requests from the PCI bus or the TM3260 targeting the MMIO aperture converge
to the DCS bus through the MMIO apertures and then are dispatched to the
corresponding MMIO registers.
Requests from the TM3260 to the APERT1 aperture are transferred to the DCS
bus and then dispatched to the PCI module if the address of the request matches
one of the three apertures, PCI2, PCI1 or XIO. These apertures are used to map
loads and stores from the CPU to any slave connected to the PCI bus. The
definition of the MMIO registers containing the address ranges for the two
internal PCI apertures can be found in
DCS_DRAM_LO
PCI_BASE1_LO
PCI_BASE2_LO
DCS_DRAM_HI
PCI_BASE2_HI
PCI_BASE1_HI
0x1 0000 0000
0x0000 0000
Rev. 3 — 17 March 2006
base_14
base_18
2MB
DRAM Aperture
MMIO Aperture
PCI1 Aperture
PCI2 Aperture
XIO Aperture
inaccessible
inaccessible
inaccessible
inaccessible
DCS
Chapter 7 PCI-XIO
Chapter 3: System On Chip Resources
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
2MB
PNX15xx Series
DRAM Aperture
MMIO Aperture
PCI1 Aperture
PCI2 Aperture
XIO Aperture
inaccessible
inaccessible
inaccessible
inaccessible
PCI
Module.
0x1 0000 0000
0x0000 0000
BASE_14
BASE_18
BASE_10
3-4