Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 101

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

86
UM005003-0703
A0
D0
INT1,2
MREQ
Z8018x
Family MPU User Manual
–
IORQ
–
A19
WR
Phi
M1
RD
D7
ST
Last MC
Dynamic RAM Refresh Control
MC: Machine Cycle
Figure 43.
The Z8X180 incorporates a dynamic RAM refresh control circuit
including 8-bit refresh address generation and programmable refresh
timing. This circuit generates asynchronous refresh cycles inserted at the
programmable interval independent of CPU program execution. For
systems which do not use dynamic RAM, the refresh function can be
disabled.
When the internal refresh controller determines that a refresh cycle should
occur, the current instruction is interrupted at the first breakpoint between
machine cycles. The refresh cycle is inserted by placing the refresh
address on A0–A7 and the RFSH output is driven Low.
T1
T2
INT1, INT2, internal interrupt acknowledge cycle
TW*
PC
TW*
INT1, INT2 and Internal Interrupts Timing Diagram
T3
Ti
T1
T2
SP-1
PCH
PC Stacking
T3
T1
T2
SP-2
PCL
T3
T1
* Two Wait States are automatically inserted.
Vector
T2
address (L)
Vector Table Read
Starting
T3
T1
Vector+1
T2
address (H)
Starting
T3
T1
Op Code
fetch cycle
Starting
Address
T2
T3