Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 113

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

98
UM005003-0703
Bit
Position Bit/Field R/W
3
1
–
Z8018x
Family MPU User Manual
2
SM1:0
MMOD
Table 12.
DM1
0
0
1
1
W
R/W
DM0
0
1
0
1
Channel 0 Destination
Value
Memory/I/O
Memory
Memory
Memory
I/O
Description
Source Mode Channel — Specifies whether the source
for channel 0 transfers is memory, I/O, or memory
mapped I/O and the corresponding address modifier.
Reference Table 13.
DMA Memory Mode Channel 0 — When channel 0 is
configured for memory to/from memory transfers, the
external
timing. Instead, two automatic transfer timing modes are
selectable - BURST (MMOD is 1) and CYCLE STEAL
(MMOD is 0). For BURST memory to/from memory
transfers, the DMAC takes control of the bus
continuously until the DMA transfer completes (as shown
by the byte count register is 0). In CYCLE STEAL mode,
the CPU is given a cycle for each DMA byte transfer
cycle until the transfer is completed.
For channel 0 DMA with I/O source or destination, the
DREQ
ignored.
0 input times the transfer and thus MMOD is
DREQ
0 input is not used to control the transfer
Address Increment/Decrement
+ 1
-1
fixed
fixed