Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 192

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

Flag Registers (F, F')
The flag registers store status bits (described in the next section) resulting
from executed instructions.
General Purpose Registers (BC, BC', DE, DE', HL, HL')
The General Purpose Registers are used for both address and data
operation. Depending on the instruction, each half (8 bits) of these
registers (B, C, D, E, H, and I) may also be used.
Interrupt Vector Register (I)
For interrupts that require a vector table address to be calculated (INT0
Mode 2, INT1, INT2, and internal interrupts), the Interrupt Vector
Register (I) provides the most significant byte of the vector table address.
I is cleared to
R Counter (R)
The least significant seven bits of the R counter (R) count the number of
instructions executed by the Z80180. R increments for each CPU Op Code
fetch cycle (each M1 cycle). R is cleared to
Index Registers (IX, and IY)
The Index Registers are used for both address and data operations. For
addressing, the contents of a displacement specified in the instruction are
added to or subtracted from the Index Register to determine an effective
operand address.
00H
during reset.
Family MPU User Manual
00H
during reset.
UM005003-0703
Z8018x
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