Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 153

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

138
ASCI1 Time Constant Low Register (I/O Address: 1CH) (Z8S180/L180-Class Processors
Only)
ASCI1 Time Constant High Register (I/O Address: 1DH) (Z8S180/L180-Class Processors
Only)
UM005003-0703
Bit
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Z8018x
Family MPU User Manual
R/W
R/W
7
0
7
0
Modem Control Signals
ASCI channel 0 has CTS0, DCD0 and RTS0 external modem control
signals. ASCI channel 1 has a CTS1 modem control signal which is
multiplexed with Clocked Serial Receive Data (RXS).
CTS0: Clear to Send 0 (Input)
The CTS0 input allows external control (start/stop) of ASCI channel 0
transmit operations. When CTS0 is High, the channel 0 TDRE bit is held
at
When CTS0 is Low, TDRE reflects the state of TDR0. The actual
transmit operation is not disabled by CT High, only TDRE is inhibited:
DCD0: Data Carrier Detect 0 (Input)
The DCD0 input allows external control (start/stop) of ASCI channel 0
receive operations. When DCD0 is High, the channel 0 RDRF bit is held
at 0 whether or not the RDR0, (Receive Data Register) is full or empty.
0
whether or not the TDR0 (Transmit Data Register) is full or empty.
R/W
R/W
6
6
0
0
R/W
R/W
5
0
5
0
R/W
R/W
4
4
0
0
R/W
R/W
3
0
3
0
R/W
R/W
2
2
0
0
R/W
R/W
1
0
1
0
R/W
R/W
0
0
0
0