Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 75

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

60
MMU Common/Bank Area Register (CBAR: 3AH)
UM005003-0703
Bit
Bit/Field
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field R/W
7
3
–
–
Z8018x
Family MPU User Manual
4
0
MMU Register Description
CA7
BA3
CA3
R/W
–
–
4
0
7
1
MMU Common/Bank Area Register (CBAR)
CBAR specifies boundaries within the Z8X180 64KB logical address
space for up to three areas; Common Area 0, Bank Area and Common
Area 1.
R/W
R/W
CA2
R/W
6
1
Value
CA1
R/W
5
1
Description
CA specifies the start (low) address (on 4KB boundaries)
for the Common Area 1. This also determines the last
address of the Bank Area.
BA specifies the start (low) address (on 4KB boundaries)
for the Bank Area. This also determines the last address
of the Common Area 0.
CA0
R/W
4
1
BA3
R/W
3
0
BA2
R/W
2
0
BA1
R/W
1
0
BA0
R/W
0
0