Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 211

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

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Z8018x
Family MPU User Manual
Symbol Item
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Ef
TOD
STDI
STDE
SRSI
SRHI
SRSE
SRHE
RES
REH
OSC
EXR
EXF
RR
RF
Table 31.
Enable Fall Time
PHI Fall to Timer Output Delay
CSI/O Transmit Data Delay Time
(Internal Clock Operation)
CSI/O Transmit Data Delay Time
(External Clock Operation)
CSI/O Receive Data Set-up Time
(Internal Clock Operation)
CSI/O Receive Data Hold Time
(Internal Clock Operation)
CSI/O Receive Data Set-up Time
(External Clock Operation)
CSI/O Receive Data Hold Time
(External Clock Operation)
RESET Set-up Time to PHI Fall
RESET Hold Time from PHI Fall
Oscillator Stabilization Time
External Clock Rise Time (EXTAL) —
External Clock Fall Time (EXTAL)
RESET Rise Time
RESET Fall Time
V
Operation
Z8S180 AC Characteristics (Continued) V
DD
= 3.3V ±10%; 33-MHz Characteristics Apply Only to 5V
Min
—
—
—
—
1
1
1
1
40
25
—
—
—
—
Z8S180—20
MHz
Max
10
75
2
7.5 t
C
+75
—
—
—
—
—
5
5
50
50
—
20
CY
Min
—
—
—
—
1
1
1
1
25
15
—
—
—
—
—
Z8S180—33
DD
MHz
= 5V ±10% or
Max
10
50
2
75 t
+60
—
—
—
—
—
—
20
5
5
50
50
CYC
Unit
ns
ns
tcyc
ns
tcyc
tcyc
tcyc
tcyc
ns
ns
ns
ns
ns
ms
ms