Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 122
Z8018010PSG
Manufacturer Part Number
Z8018010PSG
Description
IC 10MHZ Z180 CMOS ENH MPU 64DIP
Manufacturer
Zilog
Specifications of Z8018010PSG
Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
64-DIP (0.750", 19.05mm)
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
64
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
8018010
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3889
Z8018010PSG
Z8018010PSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8018010PSG
Manufacturer:
Zilog
Quantity:
40
- Current page: 122 of 326
- Download datasheet (5Mb)
DREQ0
Phi
Memory to I/O (Memory Mapped I/O) — Channel 0
For memory to/from I/O (and memory to/from memory mapped I/O) the
DREQ0 input is used to time the DMA transfers. In addition, the TEND0
(Transfer End) output is used to indicate the last (byte count register
BCR0 =
The DREQ0 input can be programmed as level- or edge-sensitive.
When level-sense is programmed, the DMA operation begins when
DREQ0 is sampled Low. If DREQ0 is sampled High, after the next DMA
byte transfer, control is relinquished to the Z8X180 CPU. As illustrated in
Figure 47, DREQ0 is sampled at the rising edge of the clock cycle prior to
T3, (that is, either T2 or Tw).
Figure 47.
When edge-sense is programmed, DMA operation begins at the falling
edge of DREQ0 If another falling edge is detected before the rising edge
of the clock prior to T3 during DMA write cycle (that is T2 or Tw), the
DMAC continues operating. If an edge is not detected, the CPU is given
control after the current byte DMA transfer completes. The CPU
continues operating until a DREQ0 falling edge is detected before the
Tw
DMA
Write
Cycle
Tw
**
T3
00H
CPU Operation and DMA Operation DREQ0 is Programmed
for Level-Sense
T1
) transfer.
CPU
Machine
Cycle
T2
**
T3
T1
DMA
Read
Cycle
T2
T3
T1
** DREQ0 is sampled at
T2
DMA
Write
Cycle (I/O)
Family MPU User Manual
Tw Tw
**
T3
T1
UM005003-0703
T2
Z8018x
107
Related parts for Z8018010PSG
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Microprocessor Unit
Manufacturer:
ZiLOG Semiconductor
Datasheet:
Part Number:
Description:
Z80180 EMULATOR
Manufacturer:
Zilog
Datasheet:
Part Number:
Description:
Z80180, Z8s180, Z8l180 Mpu Operation
Manufacturer:
ZiLOG Semiconductor
Datasheet:
Part Number:
Description:
Communication Controllers, ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP)
Manufacturer:
Zilog, Inc.
Datasheet:
Part Number:
Description:
KIT DEV FOR Z8 ENCORE 16K TO 64K
Manufacturer:
Zilog
Datasheet:
Part Number:
Description:
KIT DEV Z8 ENCORE XP 28-PIN
Manufacturer:
Zilog
Datasheet:
Part Number:
Description:
DEV KIT FOR Z8 ENCORE 8K/4K
Manufacturer:
Zilog
Datasheet:
Part Number:
Description:
KIT DEV Z8 ENCORE XP 28-PIN
Manufacturer:
Zilog
Datasheet:
Part Number:
Description:
DEV KIT FOR Z8 ENCORE 4K TO 8K
Manufacturer:
Zilog
Datasheet:
Part Number:
Description:
CMOS Z8 microcontroller. ROM 16 Kbytes, RAM 256 bytes, speed 16 MHz, 32 lines I/O, 3.0V to 5.5V
Manufacturer:
Zilog, Inc.
Datasheet:
Part Number:
Description:
Low-cost microcontroller. 512 bytes ROM, 61 bytes RAM, 8 MHz
Manufacturer:
Zilog, Inc.
Datasheet:
Part Number:
Description:
Z8 4K OTP Microcontroller
Manufacturer:
Zilog, Inc.
Datasheet:
Part Number:
Description:
CMOS SUPER8 ROMLESS MCU
Manufacturer:
Zilog, Inc.
Datasheet:
Part Number:
Description:
SL1866 CMOSZ8 OTP Microcontroller
Manufacturer:
Zilog, Inc.
Datasheet: