Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 324

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

308
Memory and I/O Wait state insertion
Memory management unit (MMU)
Memory to ASCI
Memory to memory
MMU Register description
Mode
Modem control signals
N
NMI
Non-maskable interrupt
O
On-chip clock generator
Operation modes
UM005003-0703
Z8018x
Family MPU User Manual
HALT
IOSTOP
SLEEP
SYSTEM STOP
and DMA operation timing diagram
Use
Circuit board design rules
External clock interface
Operating frequencies
Control register
CPU timing
IOC
M1 Enable
M1 temporary enable
74
16
31
33
35
15
18
109
105
84
35
138
72
16
168
60
169
170
13
29
115
P
Pin description
Pin package
Programmable reload timer (PRT)
Programming
PRT
R
Refresh
Register
A0 through CTS1
BUSREQ through RFSH
D0 through INT2
RTS0 through TEND1
TEST through XTAL
64-pin DIP
68-pin PLCC
80-pin QFP
Level-sense
Block diagram
Bus release mode timing diagram
Interrupt request generation
Timer control register
Control register
ASCI Control A0
ASCI Control A1
ASCI Control B
ASCI Status 0
ASCI Status 1
87
3
5
109
4
120
123
157
88
131
8
125
128
7
10
161
10
9
164
14
167