Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 23

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

8
UM005003-0703
Z8018x
Family MPU User Manual
D0–D7. Data Bus (Bidirectional, Active High, 3-state). D0-D7 constitute
an 8-bit bidirectional data bus, used for the transfer of information to and
from I/O and memory devices. The data bus enters the high impedance
state during RESET and external bus acknowledge cycles.
DCD0. Data Carrier Detect 0 (Input, Active Low). This input is a
programmable modem control signal for ASCI channel 0.
DREQ0, DREQ1. DMA Request 0 and 1 (Input, Active Low). DREQ is
used to request a DMA transfer from one of the on-chip DMA channels.
The DMA channels monitor these inputs to determine when an external
device is ready for a read or write operation. These inputs can be
programmed to be either level- or edge-sensed. DREQ0 is multiplexed
with CKA0.
E. Enable Clock (Output, Active High). Synchronous machine cycle clock
output during bus transactions.
EXTAL. External Clock/Crystal (Input, Active High). Crystal oscillator
connection. An external clock can be input to the Z8X180 on this pin
when a crystal is not used. This input is Schmitt-triggered.
HALT. Halt/Sleep Status (Output, Active Low). This output is asserted
after the CPU has executed either the HALT or SLP instruction, and is
waiting for either non-maskable or maskable interrupt before operation
can resume. HALT is also used with the M1 and ST signals to decode
status of the CPU machine cycle.
INT0. Maskable Interrupt Request 0 (Input, Active Low). This signal is
generated by external I/O devices. The CPU honors this request at the end
of the current instruction cycle as long as the NMI and BUSREQ signals
are inactive. The CPU acknowledges this interrupt request with an
interrupt acknowledge cycle. During this cycle, both the M1 and IORQ
signals become Active.
INT1, INT2. Maskable Interrupt Requests 1 and 2 (Inputs, Active Low).
This signal is generated by external I/O devices. The CPU honors these
requests at the end of the current instruction cycle as long as the NMI,