Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 25

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

10
UM005003-0703
Z8018x
Family MPU User Manual
RTS0. Request to Send 0 (Output, Active Low). This output is a
programmable modem control signal for ASCI channel 0.
RXA0, RXA1. Receive Data 0 and 1 (Inputs, Active High). These signals
are the receive data to the ASCI channels.
RXS. Clocked Serial Receive Data (Input, Active High). This line is the
receiver data for the CSIO channel. RXS is multiplexed with the CTS1
signal for ASCI channel 1.
ST. Status (Output, Active High). This signal is used with the M1 and
HALT output to decode the status of the CPU machine cycle. Table 1
provides status summary.
Table 1.
TEND0, TEND1. Transfer End 0 and 1 (Outputs, Active Low). This
output is asserted active during the last write cycle of a DMA operation. It
is used to indicate the end of the block transfer. TEND0 in multiplexed
with CKA1.
TEST. Test (Output, not on DIP version). This pin is for test and must be
left open.
ST
0
1
1
0
0
1
1. X = Don't care
2. MC = Machine cycle
HALT
1
1
1
X
0
0
1
Status Summary
M1
0
0
1
1
0
1
Operation
CPU operation (1st Op Code fetch)
CPU operation (2nd Op Code and 3rd Op Code fetch)
CPU operation (MC
DMA operation
HALT mode
SLEEP mode (including SYSTEM STOP mode)
2
except for Op Code fetch)