Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 87

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

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UM005003-0703
A0
D0
Z8018x
Family MPU User Manual
MREQ
–
–
A19
WR
Phi
RD
D7
MI
T1 T2 T3
3rd Op Code
Fetch Cycle
Undefined
Op Code
Figure 33.
External Interrupts
The Z8X180 features four external hardware interrupt inputs:
•
•
•
•
NMI, INT1, and INT2 feature fixed interrupt response modes. INT0 has 3
different software programmable interrupt response modes—Mode 0,
Mode 1 and Mode 2.
NMI - Non-Maskable Interrupt
The
software. When
PC
NMI–Non-maskable interrupt
INT0–Maskable Interrupt Level 0
INT1–Maskable Interrupt Level 1
INT2–Maskable Interrupt Level 2
NMI
T1 T2 TTP
interrupt input is edge-sensitive and cannot be masked by
Read Cycle
Memory
TRAP Timing - 3rd Op Code Undefined
IX+d, IY+d
NMI
T3
is detected, the Z8X180 operates as follows:
T1
Ti
Ti
Ti
T1
T2
SP-1
PCH
PC stacking
T3
T1 T2
SP-2
PCL
T3
T1 T2 T3
Restart from 0000H
Op Code
fetch cycle
0000H