Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 50

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

INT1, NMI
A0
Figure 21.
IOSTOP Mode
IOSTOP mode is entered by setting the IOSTOP bit of the I/O Control
Register (ICR) to
operating. However, the CPU continues to operate. Recovery from
IOSTOP mode is by resetting the IOSTOP bit in ICR to
SYSTEM STOP Mode
SYSTEM STOP mode is the combination of SLEEP and IOSTOP modes.
SYSTEM STOP mode is entered by setting the IOSTOP bit in ICR to
followed by execution of the SLP instruction. In this mode, on-chip I/O
and CPU stop operating, reducing power consumption. Recovery from
SYSTEM STOP mode is the same as recovery from SLEEP mode, noting
that internal I/O sources, (disabled by IOSTOP) cannot generate a
recovery interrupt.
Phi
HALT
M1
–
A19
SLP 2nd Op Code
Fetch Cycle
T2
SLP 2nd Op Code address
SLEEP Timing Diagram
T3
1
. In this case, on-chip I/O (ASCI, CSI/O, PRT) stops
T1
T2
SLEEP mode
TS
FFFFFH
Family MPU User Manual
TS
T1
Op Code Fetch or Interrupt
Acknowledge Cycle
T2
0
UM005003-0703
.
Z8018x
T3
1
35