Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 129

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

114
UM005003-0703
Z8018x
Family MPU User Manual
DMAC Internal Interrupts
Figure 50 illustrates the internal DMA interrupt request generation circuit.
Figure 50.
DE0 and DE1 are automatically cleared to
completion (byte count is
channel 1, respectively. They remain
and DE1 use level sense, an interrupt occurs if the CPU IEF1 flag is set to
1
further DMA interrupts (by programming the channel DIE bit is
enabling CPU interrupts (for example, IEF1 is set to
the DMAC address and count registers, the DIE bit can be set to
reenable the channel interrupt, and at the same time DMA can resume by
programming the channel DE bit =
DMAC and NMI
NMI, unlike all other interrupts, automatically disables DMAC operation
by clearing the DME bit of DSTAT. Thus, the NMI interrupt service
routine responds to time-critical events without delay due to DMAC bus
usage. Also, NMI can be effectively used as an external DMA abort input,
recognizing that both channels are suspended by the clearing of DME.
DIE0
DIE1
DE0
. Therefore, the DMA termination interrupt service routine disables
DE1
DMA Interrupt Request Generation
0
) of a DMA operation for channel 0 and
IEF1
1
.
0
until a
0
by the Z8X180 at the
1
is written. Because DE0:
DMA ch1 Interrupt
Request
DMA ch0 Interrupt
Request
1
). After reloading
0
1
) before
to