Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 120

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

In addition, the operation of channel 0 DMA with the on-chip ASCI
(Asynchronous Serial Communication Interface) as well as Channel 1
DMA are described.
Memory to Memory—Channel 0
For memory to/from memory transfers, the external DREQ0 input is not
used for DMA transfer timing. Rather, the DMA operation is timed in one
of two programmable modes – BURST or CYCLE STEAL. In both
modes, the DMA operation automatically proceeds until termination
(shown by byte count-BCR0) =
In BURST mode, the DMA operation proceeds until termination. In this
case, the CPU cannot perform any program execution until the DMA
operation is completed. In CYCLE STEAL mode, the DMA and CPU
operation are alternated after each DMA byte transfer until the DMA is
completed. The sequence:
•
•
is repeated until DMA is completed. Figure 46 describes CYCLE STEAL
mode DMA timing.
1 CPU Machine Cycle
DMA Byte Transfer
0
.
Family MPU User Manual
UM005003-0703
Z8018x
105