Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 134
Z8018010PSG
Manufacturer Part Number
Z8018010PSG
Description
IC 10MHZ Z180 CMOS ENH MPU 64DIP
Manufacturer
Zilog
Specifications of Z8018010PSG
Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
64-DIP (0.750", 19.05mm)
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
64
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
8018010
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3889
Z8018010PSG
Z8018010PSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8018010PSG
Manufacturer:
Zilog
Quantity:
40
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ASCI Receive Data Register Ch. 0 (RDR0: 08H)
ASCI Receive Data Register Ch. 1 (RDR1: 09H)
Bit
Bit/Field
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Bit/Field
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
7
7
ASCI Receive Shift Register 0,1(RSR0, 1)
This register receives data shifted in on the RXA pin. When full, data is
automatically transferred to the ASCI Receive Data Register (RDR) if it
is empty. If RSR is not empty when the next incoming data byte is shifted
in, an overrun error occurs. The RSR is not program-accessible.
ASCI Receive Data Register 0,1 (RDR0, 1: I/O Address =
When a complete incoming data byte is assembled in RSR, it is
automatically transferred to the RDR if RDR is empty. The next incoming
data byte can be shifted into RSR while RDR contains the previous
received data byte. Thus, the ASCI receiver on Z80180 is double-
buffered.
\
On the Z8S180 and Z8L180-class processors are quadruple buffered. The
ASCI Receive Data Register is a read-only register. However, if RDRF =
6
6
5
5
ASCI Receive Channel 0
ASCI Receive Channel 1
4
4
R/W
R/W
0
0
3
3
Family MPU User Manual
2
2
1
1
UM005003-0703
08H
Z8018x
0
0
,
09H
)
119
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