Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 91

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

76
UM005003-0703
Z8018x
Family MPU User Manual
A0
D0
Note:
MREQ
Figure 36.
INT0 Mode 1
When INT0 is received, the PC is stacked and instruction execution
restarts at logical address
IORQ
–
INT0
–
A19
WR
Phi
RD
M1
D7
The TRAP interrupt occurs if an invalid instruction is fetched
during Mode 0 interrupt acknowledge. (Reference Figure 36.)
Last MC
INT0 Mode 0 Timing Diagram
MC: Machine Cycle
T1
INT0 acknowledge cycle
0038H
T2
TW
*
. Both IEF1 and IEF2 flags are reset to
RST instruction
TW
*
PC
T3
Ti
*Two Wait States are automatically inserted
Ti
RST instruction execution
T1
PC is pushed onto stack
T2
SP-1
PCH
T3
T1
SP-2
T2
PCL
0
T3
,