Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 86

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

A0
D0
MREQ
–
–
A19
WR
Phi
RD
D7
MI
stacked PC-1. If UFO is
equal to the stacked PC-2.
Bus Release cycle, Refresh cycle, DMA cycle, and WAIT cycle cannot be
inserted just after TTP state which is inserted for TRAP interrupt
sequence. Figure depicts TRAP Timing - 2nd Op Code undefined and
Figure illustrates Trap Timing - 3rd Op Code undefined.
Figure 32.
T1
2nd Op Code
Fetch Cycle
T2
Undefined
Op Code
T3
TRAP Timing Diagram -2nd Op Code Undefined
PC
Ti
Ti
Ti
1
, the starting address of the invalid instruction is
Ti
Ti
T1
T2
SP-1
PCH
PC Stacking
T3
Family MPU User Manual
T1
T2
SP-2
PCL
T3
Restart from 0000H
UM005003-0703
T1
Op Code
Fetch Cycle
T2
0000H
Z8018x
T3
71