Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 85

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

70
UM005003-0703
Z8018x
Family MPU User Manual
Table 8.
TRAP Interrupt
The Z8X180 generates a non-maskable (not affected by the state of IEF1)
TRAP interrupt when an undefined Op Code fetch occurs. This feature
can be used to increase software reliability, implement an extended
instruction set, or both. TRAP may occur during Op Code fetch cycles
and also if an undefined Op Code is fetched during the interrupt
acknowledge cycle for INT0 when Mode 0 is used.
When a TRAP interrupt occurs the Z8X180 operates as follows:
1. The TRAP bit in the Interrupt TRAP/Control (ITC) register is set to
2. The current PC (Program Counter) value, reflecting location of the
3. The Z8X180 vectors to logical address 0. Note that if logical address
The state of the UFO (Undefined Fetch Object) bit in ITC allows TRAP
manipulation software to correctly adjust the stacked PC, depending on
whether the second or third byte of the Op Code generated the TRAP. If
UFO is
CPU
Operation
DI
LD A, I
LID A, R
undefined Op Code, is saved on the stack.
0000H
as for RESET. In this case, testing the TRAP bit in ITC reveals
whether the restart at physical address
RESET or TRAP.
0
, the starting address of the invalid instruction is equal to the
State of IEF1 and IEF2 (Continued)
is mapped to physical address
IEF1
0
not affected not affected Transfers the contents of IEF1 to
not affected not affected Transfers the contents of IEF1 to
IEF2
0
00000H
REMARKS
P/V
P/V
00000H
. the vector is the same
was caused by
1
.