Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 81

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

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UM005003-0703
Z8018x
Family MPU User Manual
Note:
Interrupt Vector Register (I)
Mode 2 for INT0 external interrupt, INT1 and INT2 external interrupts,
and all internal interrupts (except TRAP) use a programmable vectored
technique to determine the address at which interrupt processing starts. In
response to the interrupt a 16-bit address is generated. This address
accesses a vector table in memory to obtain the address at which
execution restarts.
While the method for generation of the least significant byte of the table
address differs, all vectored interrupts use the contents of I as the most
significant byte of the table address. By programming the contents of I,
vector tables can be relocated on 256 byte boundaries throughout the
64KB logical address space.
Interrupt Vector Low Register
This register determines the most significant three bits of the low-order
byte of the interrupt vector table address for external interrupts INT1 and
INT2 and all internal interrupts (except TRAP). The five least significant
bits are fixed for each specific interrupt source. By programming IL, the
Function
Interrupt Vector High
Interrupt Vector Low
Interrupt/Trap Control
Interrupt Enable Flag 1,2 IEF1, IEF2 El and DI
I is read/written with the LD A, I and LD I, A instructions rather
than I/O (IN, OUT) instructions. I is initialized to
RESET.
Name
I
IL
ITC
Access Method
LD A,I and LD I, A instructions
I/O instruction (addr = 33H)
I/O instruction (addr = 34H)
00H
during