LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 118
LPC1343FHN33,551
Manufacturer Part Number
LPC1343FHN33,551
Description
IC MCU 32BIT 32KB FLASH 33HVQFN
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1343FHN33,551
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
Development Tools By Supplier
OM11039, OM11040, OM11046, OM11048
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
33HVQFN EP
Device Core
ARM Cortex M3
Family Name
LPC1000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4944
935289655551
935289655551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1343FHN33,551
Manufacturer:
NXP
Quantity:
780
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NXP Semiconductors
Table 140. Register overview: GPIO (base address port 0: 0x5000 0000; port 1: 0x5001 0000, port 2: 0x5002 0000;
UM10375
User manual
Name
GPIOnDATA
GPIOnDATA
-
GPIOnDIR
GPIOnIS
GPIOnIBE
GPIOnIEV
GPIOnIE
GPIOnRIS
GPIOnMIS
GPIOnIC
-
port 3: 0x5003 0000)
8.4.1 GPIO data register
The GPIOnDATA register holds the current state of the pin (HIGH or LOW), independently
of whether the pin is configured as an GPIO input or output or as another digital function.
If the pin is configured as GPIO output, the current value of the GPIOnDATA register is
driven to the pin.
Table 141. GPIOnDATA register (GPIO0DATA, address 0x5000 3FFC; GPIO1DATA, address
A read of the GPIOnDATA register always returns the current logic level (state) of the pin
independently of its configuration. Because there is a single data register for both the
value of the output driver and the state of the pin’s input, write operations have different
effects depending on the pin’s configuration:
Bit
11:0
31:12
•
•
If a pin is configured as GPIO input, a write to the GPIOnDATA register has no effect
on the pin level. A read returns the current state of the pin.
If a pin is configured as GPIO output, the current value of GPIOnDATA register is
driven to the pin. This value can be a result of writing to the GPIOnDATA register, or it
can reflect the previous state of the pin if the pin is switched to GPIO output from
GPIO input or another digital function. A read returns the current state of the pin.
Symbol
DATA
-
Access
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
R
R
W
-
0x5001 3FFC; GPIO2DATA, address 0x5002 3FFC; GPIO3DATA, address 0x5003
3FFC) bit description
All information provided in this document is subject to legal disclaimers.
Address offset
0x0000 to 0x3FF8
0x3FFC
0x4000 to 0x7FFC
0x8000
0x8004
0x8008
0x800C
0x8010
0x8018
0x801C
0x8014
0x8020 - 0xFFFF
Description
0.
Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW =
Reserved
Rev. 2 — 7 July 2010
Chapter 8: LPC13xx General Purpose I/O (GPIO)
Description
Port n data address masking register
locations for pins PIOn_0 to PIOn_11 (see
Section
Port n data register for pins PIOn_0 to
PIOn_11
Reserved
Data direction register for port n
Interrupt sense register for port n
Interrupt both edges register for port n
Interrupt event register for port n
Interrupt mask register for port n
Raw interrupt status register for port n
Masked interrupt status register for port n
Interrupt clear register for port n
Reserved
8.5.1)
UM10375
© NXP B.V. 2010. All rights reserved.
Reset
value
n/a
0x00
-
Reset
value
n/a
n/a
-
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Access
R/W
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