LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 223
LPC1343FHN33,551
Manufacturer Part Number
LPC1343FHN33,551
Description
IC MCU 32BIT 32KB FLASH 33HVQFN
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1343FHN33,551
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
Development Tools By Supplier
OM11039, OM11040, OM11046, OM11048
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
33HVQFN EP
Device Core
ARM Cortex M3
Family Name
LPC1000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4944
935289655551
935289655551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1343FHN33,551
Manufacturer:
NXP
Quantity:
780
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UM10375
User manual
12.11.6.2 Data transfer after loss of arbitration
12.11.6.3 Forced access to the I
Arbitration may be lost in the master transmitter and master receiver modes (see
Figure
0x78, and 0xB0 (see
If the STA flag in I2CON is set by the routines which service these states, then, if the bus
is free again, a START condition (state 0x08) is transmitted without intervention by the
CPU, and a retry of the total serial transfer can commence.
In some applications, it may be possible for an uncontrolled source to cause a bus
hang-up. In such situations, the problem may be caused by interference, temporary
interruption of the bus or a temporary short-circuit between SDA and SCL.
If an uncontrolled source generates a superfluous START or masks a STOP condition,
then the I
obtained within a reasonable amount of time, then a forced access to the I
possible. This is achieved by setting the STO flag while the STA flag is still set. No STOP
condition is transmitted. The I
and is able to transmit a START condition. The STO flag is cleared by hardware (see
Figure
08H
Fig 34. Simultaneous Repeated START conditions from two masters
Fig 35. Forced access to a busy I
S
28). Loss of arbitration is indicated by the following states in I2STAT; 0x38, 0x68,
35).
SLA
2
STO flag
SDA line
C-bus stays busy indefinitely. If the STA flag is set and bus access is not
STA flag
SCL line
W
All information provided in this document is subject to legal disclaimers.
18H
A
Figure 30
Rev. 2 — 7 July 2010
DATA
2
C-bus
2
C hardware behaves as if a STOP condition was received
time limit
and
repeated START earlier
other Master sends
28H
2
A
C-bus
Figure
S
31).
Chapter 12: LPC13xx I2C-bus controller
OTHER MASTER
CONTINUES
condition
start
retry
08H
P
UM10375
© NXP B.V. 2010. All rights reserved.
S
2
C-bus is
SLA
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